Multiple threshold voltage trigate devices using 3d condensation

Patent metadata

Field	Value
Publication number	US-2016247731-A1
Application number	US-201514629552-A
Country	US
Kind code	A1
Filing date	Feb 24, 2015
Priority date	Feb 24, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

A method of forming a multiple threshold voltage p-channel silicon germanium trigate device using (3D) condensation. The method may include forming a first and second fin in a single semiconductor layer, where the first and second fin have similar initial widths; thinning the second fin; performing a (3D) condensation process to condense the germanium within the first and second fin; and thinning the first fin to a similar width as the second fin.

First claim

What is claimed is:

1 . A method comprising:
providing a silicon-germanium-on-insulator (SGOI) substrate, the SGOI substrate includes (from bottom to top) a substrate, an insulator layer, and a SiGe layer; forming a patterned hardmask on the SiGe layer; forming a plurality of fins in the SiGe layer by etching a trench through the SiGe layer, the trench exposes a top surface of the insulator layer, the patterned hardmask protects a top surface of the plurality of fins, the plurality of fins includes a first fin and a second fin, the first fin has a first width and the second fin has a second width, and the first width is similar to the second width; trimming the second fin to a third width by etching sidewalls of the second fin, the top of the second fin is protected by the patterned hardmask, and the first fin is protected by a first fin mask; and modulating the germanium fraction of the first and second fin using a Ge-condensation process, the patterned hardmask protects the top surface of the plurality of fins, the first fin has a fourth width and the second fin has a fifth width, and the first fin has a lower germanium concentration than the second fin.

2 . The method of claim 1 , wherein the patterned hardmask is HfO 2 .

3 . The method of claim 1 , wherein the Ge-condensation forms an oxide layer on sidewalls of the plurality of fins, and the oxide layer is SiO 2 .

4 . The method of claim 1 , further comprising:
trimming the first fin to a sixth width, the sixth width is similar to the fifth width.

5 . The method of claim 1 , wherein the first width is 20 nm, the second width is 20 nm, the third width is 16 nm, the fourth width is 12 nm, and the fifth width is 8 nm.

6 . The method of claim 1 , wherein the first fin with the first width has a germanium fraction of 25 percent, the second fin with the second width has a germanium fraction of 25 percent, the second fin with the third width has a germanium fraction of 25 percent, the first fin with the fourth width has a germanium fraction of 42 percent, and the second fin with the fifth width has a germanium fraction of 50 percent.

7 . The method of claim 1 , wherein the first width and the second width are each greater than 10 nm.

8 . A method comprising:
forming a semiconductor-on-insulator (SOI) substrate, the SOI substrate includes (from bottom to top) a substrate, a buried oxide (BOX) layer, and a semiconductor layer; forming a plurality of fins in the semiconductor layer, the plurality of fins includes a first fin and as second fin, the first fin has a first width and the second fin has a second width, and a top surface of the plurality of fins is protected by a hardmask; thinning the second fin to a third width by removing a portion of the semiconductor layer from sidewalls of the second fin; and condensing the plurality of fins using a (3D) condensation process, the top surface of the plurality of fins is protected by the hardmask, the first fin has a fourth width and the second fin has a fifth width, the fifth width is less than the third width.

9 . The method of claim 8 , wherein the semiconductor layer is SiGe.

10 . The method of claim 8 , wherein the hardmask is HfO 2 .

11 . The method of claim 8 , wherein the (3D) condensation process is a Ge-condensation process.

12 . The method of claim 8 , wherein the (3D) condensation process forms an oxide layer on sidewalls of the plurality of fins, and the oxide layer is SiO 2 .

13 . The method of claim 8 , further comprising:
trimming the first fin to a sixth width, the sixth width is similar to the fifth width.

14 . The method of claim 8 , wherein the first width is 20 nm, the second width is 20 nm, the third width is 16 nm, the fourth width is 12 nm and the fifth width is 8 nm.

15 . The method of claim 8 , wherein the first fin with the first width has a germanium fraction of 25 percent, the second fin with the second width has a germanium fraction of 25 percent, the second fin with the third width has a germanium fraction of 25 percent, the first fin with the fourth width has a germanium fraction of 42 percent, and the second fin with the fifth width has a germanium fraction of 50 percent.

16 . The method of claim 8 , wherein the first width and the second width are each greater than 10 nm.

17 . A structure comprising:
a plurality of fins on an insulator layer, the plurality of fins includes a first fin and a second fin, the plurality of fins include SiGe, the first fin has a lower germanium fraction than the second fin.

18 . The structure of claim 17 , further comprising:
a hardmask on the plurality of fins, wherein the hardmask is an oxide.

19 . The structure of claim 17 , wherein the first fin has a fourth width and the second fin has a fifth width, the fourth width is greater than the fifth width.

20 . The structure of claim 17 , wherein the first fin has a sixth width and the second fin has a fifth width, the sixth width is equal to the fifth width.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Hashemi Pouya

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title