Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10141327-B2
Application number	US-201615264994-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Mar 18, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

According to an embodiment, a semiconductor memory device comprises: an insulating layer disposed on a semiconductor substrate; a plurality of memory cell arrays being arranged three-dimensionally on the insulating layer and including a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate; and a block insulating layer covering a side surface of one of the plurality of conductive layers. A high permittivity layer is provided between the insulating layer and a lowermost layer of the plurality of conductive layers. A permittivity of the high permittivity layer is much higher than that of the insulating layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first insulating layer disposed on a semiconductor substrate;
a first semiconductor layer disposed on the semiconductor substrate;
a plurality of memory cells arranged three-dimensionally above the first insulating layer and disposed above the first semiconductor layer;
a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate;
a second insulating layer covering a side surface of a lowermost layer of the plurality of conductive layers;
an oxide layer disposed on a side surface of the first semiconductor layer and contacting the second insulating layer; and
a high permittivity layer provided between the first insulating layer and the second insulating layer, a permittivity of the high permittivity layer being higher than that of the first insulating layer and the high permittivity layer directly contacting the side surface of the first semiconductor layer.

2. The semiconductor memory device according to claim 1 , wherein the first semiconductor layer is an epitaxial layer configured from epitaxial silicon.

3. The semiconductor memory device according to claim 1 , wherein the first insulating layer contacts the side surface of the first semiconductor layer.

4. The semiconductor memory device according to claim 1 , wherein an entire film thickness of the second insulating layer, the high permittivity layer, and the first insulating layer provided between the lowermost layer of the plurality of conductive layers and the semiconductor substrate is larger than that of the second insulating layer and the oxide layer provided between the lowermost layer of the plurality of conductive layers and the first semiconductor layer.

5. The semiconductor memory device according to claim 1 , wherein a difference of an entire oxide film converted film thickness of the second insulating layer, the high permittivity layer, and the first insulating layer provided between the lowermost layer of the plurality of conductive layers and the semiconductor substrate and that of the second insulating layer and the oxide layer provided between the lowermost layer of the plurality of conductive layers and the first semiconductor layer is less than 20 percent.

6. The semiconductor memory device according to claim 1 , wherein the high permittivity layer includes aluminum, hafnium, zirconium, titanium, or tantalum.

7. The semiconductor memory device according to claim 1 , wherein the high permittivity layer and the second insulating layer include an identical material.

8. The semiconductor memory device according to claim 1 , wherein the high permittivity layer is disposed between a pair of the plurality of conductive layers adjacent in the first direction.

9. The semiconductor memory device according to claim 8 , wherein a film thickness of an insulating layer between the pair of the plurality of conductive layers adjacent in the first direction is larger than that of an insulating layer between a conductive layer and a channel body of one of the plurality of memory cells.

10. A semiconductor memory device, comprising:
a memory cell array region including:
a first insulating layer disposed on a semiconductor substrate;
a plurality of memory cells arranged along a first direction that intersects a surface of the semiconductor substrate and disposed above the first insulating layer;
a plurality of conductive layers being stacked in the first direction, and which are connected to the plurality of memory cells;
a second insulating layer covering a side surface of a lowermost layer of the plurality of conductive layers; and
a high permittivity layer provided between the first insulating layer and the lowermost layer of the plurality of conductive layers, a permittivity of the high permittivity layer being higher than that of the first insulating layer; and

a peripheral region including a transistor being disposed in a periphery of the memory cell array region,
wherein the first insulating layer is provided continuously so as to cover the memory cell array region and the peripheral region, and is disposed below a gate electrode of the transistor.

11. The semiconductor memory device according to claim 10 , wherein
an inter-layer insulating layer is provided between the plurality of conductive layers, and
an entire film thickness of the first insulating layer is larger than that of the inter-layer insulating layer.

12. The semiconductor memory device according to claim 10 , wherein the first insulating layer is configured from silicon oxide.

13. The semiconductor memory device according to claim 10 , wherein the high permittivity layer is provided continuously so as to cover the memory cell array region and the peripheral region.

14. The semiconductor memory device according to claim 10 , wherein the high permittivity layer includes aluminum, hafnium, zirconium, titanium, or tantalum.

15. The semiconductor memory device according to claim 10 , wherein the high permittivity layer and the second insulating layer include an identical material.

Assignees

• Toshiba Memory Corp

Inventors

• Sonehara Takeshi
• Kito Masaru

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L28/00

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic