Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9842856-B2
Application number	US-201615251438-A
Country	US
Kind code	B2
Filing date	Aug 30, 2016
Priority date	Mar 9, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

According to an embodiment, a semiconductor memory device comprises: a plurality of control gate electrodes stacked above a substrate; a first semiconductor layer extending in a first direction above the substrate and facing the plurality of control gate electrodes; a gate insulating layer extending in the first direction and provided between the control gate electrode and first semiconductor layer; and a second semiconductor layer positioned downwardly of the first semiconductor layer and gate insulating layer, and connected to a lower end of the first semiconductor layer and the substrate. Moreover, the first semiconductor layer comprises: a first portion contacting an upper surface of the second semiconductor layer at a position more downward than a lower end of the gate insulating layer; and a second portion connected to an upper end of the first portion, extending in the first direction, and having a different crystalline structure from the first portion.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of control gate electrodes stacked above a substrate;
a first semiconductor layer extending in a first direction above the substrate and facing the plurality of control gate electrodes;
a gate insulating layer extending in the first direction and provided between the control gate electrodes and the first semiconductor layer; and
a second semiconductor layer positioned downwardly of the first semiconductor layer and the gate insulating layer, the second semiconductor layer being connected to a lower end of the first semiconductor layer and the substrate,
wherein the first semiconductor layer comprising:
a first portion contacting an upper surface of the second semiconductor layer at a position more downward than a lower end of the gate insulating layer; and
a second portion which is connected to an upper end of the first portion, extends in the first direction and has a crystalline structure different from that of the first portion.

2. The semiconductor memory device according to claim 1 , wherein
the first portion of the first semiconductor layer is a monocrystalline layer, and
the second portion of the first semiconductor layer is configured from polycrystalline silicon.

3. The semiconductor memory device according to claim 1 , wherein
a crystal orientation of the first portion of the first semiconductor layer is aligned with a crystal orientation of the second semiconductor layer.

4. The semiconductor memory device according to claim 1 , wherein
a size of a crystal grain in the first portion of the first semiconductor layer is larger than a size of a crystal grain in the second portion.

5. The semiconductor memory device according to claim 1 , wherein
the upper end of the first portion of the first semiconductor layer is positioned above the lower end of the gate insulating layer.

6. The semiconductor memory device according to claim 1 , wherein
the first semiconductor layer further comprises a third portion provided between the first portion and the control gate electrodes and between the second portion and the control gate electrodes.

7. The semiconductor memory device according to claim 1 , further comprising
a first insulating layer whose side surface is covered by the first semiconductor layer,
wherein the first portion covers a lower end of the first insulating layer, and
the second portion covers a side surface of the first insulating layer.

8. The semiconductor memory device according to claim 1 , further comprising
a first insulating layer whose side surface is covered by the first semiconductor layer,
wherein a lower end of the first insulating layer is positioned more downwardly than the lower end of the gate insulating layer.

Assignees

• Toshiba Memory Corp

Inventors

• Okamoto Tatsuya
• Hamada Tatsufumi

Classifications

• H01L23/5283

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L29/401

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title