Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9768117-B1
Application number	US-201615210313-A
Country	US
Kind code	B1
Filing date	Jul 14, 2016
Priority date	Mar 15, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

According to one embodiment, a substrate includes a first portion and a second portion. The first portion has a columnar configuration. The second portion has an upper surface continuous with a side surface of the first portion via a corner. A plurality of electrode layers include a lowermost electrode layer opposing the side surface of the first portion above the second portion. An insulating film is provided between the side surface of the first portion and a side surface of the lowermost electrode layer, and between the upper surface of the second portion and a lower surface of the lowermost electrode layer. An angle formed between the upper surface of the second portion and the corner of the substrate on the insulating film side is greater than 90°.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first portion and a second portion, the first portion having a columnar configuration, the second portion having an upper surface continuous with a side surface of the first portion via a corner;
a stacked body provided above the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed, the electrode layers including a lowermost electrode layer opposing the side surface of the first portion above the second portion of the substrate;
an insulating film provided between the side surface of the first portion of the substrate and a side surface of the lowermost electrode layer, and between the upper surface of the second portion of the substrate and a lower surface of the lowermost electrode layer;
a semiconductor body extending in a stacking direction through the stacked body and contacting the first portion of the substrate; and
a charge storage portion provided between the semiconductor body and the electrode layers upper than the lowermost electrode layer,
an angle formed between the upper surface of the second portion of the substrate and the corner of the substrate on the insulating film side being greater than 90°.

2. The semiconductor device according to claim 1 , wherein the corner of the substrate is curved.

3. The semiconductor device according to claim 2 , wherein the insulating film includes a corner portion being rounded along the corner of the substrate.

4. The semiconductor device according to claim 1 , wherein the corner of the substrate is tilted with respect to the side surface of the first portion and the upper surface of the second portion.

5. The semiconductor device according to claim 4 , wherein the insulating film includes a corner portion tilted along the corner of the substrate.

6. The semiconductor device according to claim 1 , wherein a curvature of the corner of the substrate is smaller than a curvature of a corner between the lower surface and the side surface of the lowermost electrode layer.

7. The semiconductor device according to claim 1 , wherein the insulating film contains silicon oxide.

8. The semiconductor device according to claim 1 , wherein the first portion and the second portion are a p-type silicon region.

9. The semiconductor device according to claim 8 , wherein a p-type impurity concentration of the first portion and the second portion is higher than 1×10 15 cm −3 .

10. The semiconductor device according to claim 1 , wherein a distance between the lowermost electrode layer and a second lowermost electrode layer is greater than a distance between other electrode layers.

11. The semiconductor device according to claim 1 , further comprising an interconnect portion extending in the stacking direction and contacting the second portion of the substrate.

12. The semiconductor device according to claim 1 , wherein a thickness of the insulating film provided between the upper surface of the second portion of the substrate and the lower surface of the lowermost electrode layer is thicker than a thickness of the insulating film provided between the side surface of the first portion of the substrate and the side surface of the lowermost electrode layer.

13. The semiconductor device according to claim 1 , wherein a first extension line downward from the side surface of the lowermost electrode layer intersects the corner of the substrate.

14. The semiconductor device according to claim 13 , wherein a thickness of the insulating film along the first extension line is thinner than a thickness of the insulating film provided between the upper surface of the second portion of the substrate and the lower surface of the lowermost electrode layer.

15. The semiconductor device according to claim 1 , wherein the corner of the substrate is positioned on a side more proximal to the lowermost electrode layer than to a second extension line downward from the side surface of the first portion of the substrate.

Assignees

• Toshiba Memory Corp

Inventors

• Naito Shinya
• KAKEGAWA Takayuki

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title