Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof

Patent metadata

Field	Value
Publication number	US-9748266-B1
Application number	US-201615215080-A
Country	US
Kind code	B1
Filing date	Jul 20, 2016
Priority date	Jul 20, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein a bottommost electrically conductive layer comprises a select gate electrode of a select field effect transistor of the memory device;
memory stack structures extending through the alternating stack, each of the memory stack structures comprising a memory film and a vertical semiconductor channel;
a horizontal semiconductor channel of the select field effect transistor underlying the select gate electrode; and
a gate dielectric layer contacting the top surface of the horizontal semiconductor channel, and comprising from bottom to top, a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer.

2. The three-dimensional memory device of claim 1 , wherein:
the tunneling gate dielectric layer comprises a material selected from silicon oxide and silicon oxynitride; and
the charge trapping gate dielectric layer comprises silicon nitride.

3. The three-dimensional memory device of claim 1 , wherein the memory film comprises a different layer stack than the gate dielectric layer.

4. The three-dimensional memory device of claim 1 , wherein:
the memory film comprises a stack, from outside to inside, of a blocking dielectric layer, a memory material layer, and a tunneling dielectric layer that differs from the tunneling gate dielectric layer by at least one of composition and thickness; and
the memory material layer differs from the charge trapping gate dielectric layer by at least one of composition and thickness.

5. The three-dimensional memory device of claim 1 , wherein:
the select field effect transistor comprises a source side select field effect transistor of a vertical NAND string; and
charges stored in the charge trapping gate dielectric layer increase the threshold voltage of the horizontal channel of the source side select field effect transistor.

6. The three-dimensional memory device of claim 1 , wherein:
the horizontal semiconductor channel comprises a single crystalline semiconductor material; and
the vertical semiconductor channel comprises a polycrystalline semiconductor material.

7. The three-dimensional memory device of claim 6 , wherein each vertical semiconductor channel contacts an epitaxial channel portion comprising another single crystalline semiconductor material, laterally surrounded by the select gate electrode, and is laterally spaced from the select gate electrode by gate insulating layer comprising a respective tubular dielectric spacer which lacks a charge trapping dielectric layer.

8. The three-dimensional memory device of claim 7 , wherein each tubular dielectric spacer comprises a dielectric oxide of a semiconductor material of the epitaxial channel portion, and is adjoined to the cap gate dielectric layer and to a bottommost insulating layer within the alternating stack.

9. The three-dimensional memory device of claim 1 , wherein the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layers within the alternating stack, and the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack.

10. The three-dimensional memory device of claim 9 , further comprising a retro-stepped dielectric material portion contacting the stepped surfaces of the alternating stack and contacting sidewalls of the cap gate dielectric layer and the charge trapping gate dielectric layer.

11. The three-dimensional memory device of claim 1 , further comprising a backside blocking dielectric layer continuously extending from a topmost layer within the alternating stack to the gate dielectric layer and vertically spacing each neighboring pair of an electrically conductive layer and an insulating layer within the alternating stack.

12. The three-dimensional memory device of claim 1 , further comprising:
a source region located at a surface portion of the substrate and contacting the horizontal semiconductor channel; and
a backside contact via structure extending through the alternating stack and an opening in the gate dielectric layer and contacting a top surface of the source region.

13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.

14. A method of operating a three-dimensional memory device of claim 1 , comprising injecting electrical charges through the tunneling gate dielectric layer into the charge trapping gate dielectric layer by electrically biasing the select gate electrode with respect to the horizontal semiconductor channel, wherein trapped electrical charges in the charge trapping gate dielectric layer alter a threshold voltage of the horizontal semiconductor channel.

15. A method of forming a three-dimensional memory device, comprising:
providing a substrate including a semiconductor material layer in an upper portion thereof;
forming a gate dielectric layer directly on a top surface of the semiconductor material layer, wherein the gate dielectric layer includes, from bottom to top, a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer;
forming an alternating stack of insulating layers and spacer material layers over the gate dielectric layer; and
forming memory stack structures comprising a memory film and a vertical semiconductor channel through the alternating stack;

wherein:
the spacer material layers are formed as, or subsequently replaced with, electrically conductive layers;
an upper portion of the semiconductor material layer comprises a horizontal semiconductor channel for a select field effect transistor of the memory device; and
a bottommost electrically conductive layer provided upon formation of the electrically conductive layers within the alternating stack comprises a select gate electrode for the select field

Assignees

• Sandisk Technologies Llc

Inventors

• Baraskar Ashish
• Zhang Yanli
• Pang Liang
• Lu Ching-Huang
• Baenninger Matthias
• Dong Yingda

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H01L21/28282

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L21/02164

  Electricity · mapped topic