Three-dimensional memory structure having self-aligned drain regions and methods of making thereof

Patent metadata

Field	Value
Publication number	US-2016111437-A1
Application number	US-201414514925-A
Country	US
Kind code	A1
Filing date	Oct 15, 2014
Priority date	Oct 15, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region.

First claim

1 . A monolithic three-dimensional memory structure, comprising:
a stack including an alternating plurality of insulator layers and electrically conductive layers located over a substrate; a memory opening extending through the stack; a memory film and a semiconductor channel located within the memory opening, wherein the semiconductor channel includes a vertical portion that extends vertically through a subset of layers within the stack; a drain region having a same horizontal cross-sectional area as the vertical portion of the semiconductor channel, wherein the drain region includes an electrical dopant of a first conductivity type.

2 . The monolithic three-dimensional memory structure of claim 1 , wherein the drain region includes a same semiconductor material as the vertical portion of the semiconductor channel.

3 . The monolithic three-dimensional memory structure of claim 1 , further comprising:
a first dielectric liner portion in contact with the drain region; and a first conductive electrode embedded in the first dielectric liner portion.

4 . The monolithic three-dimensional memory structure of claim 3 , further comprising a second dielectric liner portion laterally spaced from the semiconductor channel by the memory film.

5 . The monolithic three-dimensional memory structure of claim 4 , further comprising a second conductive electrode embedded in the second dielectric liner portion, wherein the first dielectric liner portion and the second dielectric liner portion have a same thickness and a same composition.

6 . The monolithic three-dimensional memory structure of claim 4 , wherein a first lateral spacing between the first conductive electrode and an outer sidewall of the drain region is the same as a first lateral thickness of the first dielectric liner portion, and a second lateral spacing between the second conductive electrode and an outer sidewall of the semiconductor channel is greater than a second lateral thickness of the second dielectric liner portion.

7 . The monolithic three-dimensional memory structure of claim 6 , wherein the second lateral spacing is greater than the first lateral spacing by a thickness of the memory film.

8 . The monolithic three-dimensional memory structure of claim 6 , wherein the memory film comprises:
a tunneling dielectric; a charge trapping layer laterally surrounding the tunneling dielectric; and at least one blocking dielectric laterally surrounding the charge trapping layer, wherein the second lateral spacing is equal to a sum of the first lateral spacing, a thickness of the tunneling dielectric, a thickness of the charge trapping layer, and a thickness of the at least one blocking dielectric.

9 . The monolithic three-dimensional memory structure of claim 8 , wherein the first dielectric liner portion contacts a top surface of the at least one blocking dielectric and a top surface of the charge trapping layer.

10 . The monolithic three-dimensional memory structure of claim 8 , wherein the at least one blocking dielectric contacts a sidewall of the second dielectric liner portion and a bottom surface of the first dielectric liner portion.

11 . The monolithic three-dimensional memory structure of claim 3 , wherein a first interface between the first dielectric liner portion and a top surface of an insulator layer within the stack is within a horizontal plane that is located above a second interface between the first dielectric liner portion and the memory film.

12 . The monolithic three-dimensional memory structure of claim 3 , wherein a vertical extent of the first dielectric liner portion is greater over the memory film than over a region of the insulator layers within the stack.

13 . The monolithic three-dimensional memory structure of claim 1 , further comprising a contact via structure in contact with a top surface of the drain region.

14 . The monolithic three-dimensional memory structure of claim 13 , further comprising a dielectric material portion having a same composition as a portion of the memory film, contacting a top surface of the drain region, and laterally contacting the conductive via structure.

15 . The monolithic three-dimensional memory structure of claim 13 , wherein the conductive via structure contacts an inner sidewall of the drain region.

16 . The monolithic three-dimensional memory structure of claim 13 , further comprising a dielectric core contacting an inner sidewall of the drain region and an inner sidewall of the semiconductor channel.

17 . The monolithic three-dimensional memory structure of claim 1 , further comprising a device located over the substrate, wherein:
the device comprises a vertical NAND device located in a device region; and at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the NAND device.

18 . The monolithic three-dimensional memory structure of claim 17 , wherein:
the substrate comprises a silicon substrate; the NAND device comprises array of monolithic three dimensional NAND strings over the silicon substrate; at least one memory cell in a first device level of the array of three dimensional NAND strings is located over another memory cell in a second device level of the array of three dimensional NAND strings; the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and each NAND string comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

19 . A method of manufacturing a three-dimensional memory structure, comprising:
forming a stack of alternating layers comprising first material layers and second material layers over a substrate; forming a temporary material layer over the stack; forming a memory opening through the temporary material layer and the stack; forming a memory film and a semiconductor channel in the memory opening; forming a first backside recess by removing the temporary material layer and a portion of the memory film that adjoins the temporary material layer, wherein a portion of a sidewall of the semiconductor channel is physically exposed to the first backside recess; and introducing electrical dopants through the physically exposed portion of the sidewall of the semiconductor channel and into a portion of the semiconductor channel, which is converted into a drain region.

20 . The method of claim 19 , further comprising:
forming a trench through the temporary material layer and the stack; and removing a material of the second material layers to form second backside recesses.

21 . The method of claim 20 , further comprising simultaneously filling the first and second backside recesses with a combination of a dielectric liner and a conductive material.

22 . The method of claim 21 , wherein the first backside recess is formed prior

Assignees

• Sandisk Technologies Inc

Inventors

• Pang Liang
• Pachamuthu Jayavel
• Dong Yingda

Classifications

• H10P32/1204

  from a plasma phase · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/681

  having a compositional variation, e.g. multilayered · CPC title