Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9911752-B2
Application number	US-201615225275-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Mar 16, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a stacked body provided on the semiconductor substrate and including a plurality of electrode films being disposed to be separated from each other along a vertical direction, a first semiconductor member provided inside the stacked body and contacting the semiconductor substrate, a second semiconductor member provided on the first semiconductor member inside the stacked body, contacting the first semiconductor member and extending in the vertical direction, and an insulating film provided between the second semiconductor member and the electrode films. A configuration of a contact surface between the first semiconductor member and the second semiconductor member is convex downward.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a semiconductor substrate;
a stacked body provided on the semiconductor substrate, the stacked body comprising a plurality of electrode films, the plurality of electrode films being disposed to be separated from each other along a vertical direction;
a first semiconductor member provided inside the stacked body and contacting the semiconductor substrate;
a second semiconductor member provided on the first semiconductor member inside the stacked body, contacting the first semiconductor member and extending in the vertical direction; and
an insulating film provided between the second semiconductor member and the electrode films,
a configuration of a contact surface between the first semiconductor member and the second semiconductor member being convex downward,
the contact surface comprising an inclined region being displaced upward toward an outer side and a flat region surrounded with the inclined region, and
a first angle formed between the upper surface of the semiconductor substrate and the flat region is smaller than a second angle formed between the upper surface of the semiconductor substrate and the inclined region.

2. The device according to claim 1 , wherein
the second angle is not less than 40° and not more than 70°.

3. The device according to claim 2 , wherein
the second angle is not less 54° and not more than 55°.

4. The device according to claim 1 , wherein
a lower portion of the first semiconductor member is disposed inside the semiconductor substrate.

5. The device according to claim 1 , wherein
a crystal structure of the semiconductor substrate and a crystal structure of the first semiconductor member are continuous.

6. The device of claim 1 , wherein
an angle formed between an upper surface of the first semiconductor member and a side surface of the first semiconductor member is an acute angle.

7. The device according to claim 6 , wherein the flat region is parallel to the upper surface of the semiconductor substrate.

8. The device according to claim 6 , wherein a boundary between the inclined region and the flat region forms a ridge line.

Assignees

• Toshiba Memory Corp

Inventors

• Kashima Takayuki
• Fukuda Masahiro
• Hirotani Takashi

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title