Method of manufacturing a three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9799657-B2
Application number	US-201415302032-A
Country	US
Kind code	B2
Filing date	Jun 23, 2014
Priority date	Jun 23, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a thin layer structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate;
forming a through-hole penetrating the thin layer structure and exposing the substrate;
forming a semiconductor layer covering an inner sidewall of the through-hole, the semiconductor layer partially filling the through-hole;
oxidizing a first portion of the semiconductor layer to form a first insulating layer; and
injecting oxygen atoms into a second portion of the semiconductor layer,
wherein an oxygen atomic concentration of the second portion is lower than an oxygen atomic concentration of the first insulating layer, and
wherein oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.

2. The method of claim 1 , wherein the second portion of the semiconductor layer, which is injected with the oxygen atoms, has a higher electrical conductivity than the first insulating layer.

3. The method of claim 1 , wherein the semiconductor layer includes a poly-crystalline semiconductor material, and
wherein the oxygen atoms are injected into a grain boundary of the poly-crystalline semiconductor material.

4. The method of claim 3 , wherein the semiconductor layer is a poly-crystalline silicon layer, and
wherein the oxygen atoms are combined with silicon atoms at a grain boundary in the poly-crystalline silicon layer.

5. The method of claim 1 , wherein the oxygen atomic concentration of the second portion is in a range of 10 18 /cm 3 to 10 20 /cm 3 .

6. The method of claim 1 , wherein the oxidation process is a radical oxidation process performed at a temperature in a range of 600° C. to 1000° C.

7. The method of claim 1 , wherein the oxidation process is a wet oxidation process performed at a temperature in a range of 800° C. to 1000° C.

8. The method of claim 1 , further comprising:
forming a first semiconductor pattern between the inner sidewall of the through-hole and the semiconductor layer;
forming a second insulating layer filling a rest region of the through-hole after performing the oxidation process; and
planarizing the second insulating layer, the first insulating layer and the second portion of the semiconductor layer to form a second semiconductor pattern, a first insulating pattern and a second insulating pattern in the through-hole at the same time.

9. The method of claim 8 , further comprising:
injecting oxygen atoms into the first semiconductor pattern,
wherein injecting the oxygen atoms into the second portion of the semiconductor layer and injecting the oxygen atoms into the first semiconductor pattern are performed using the oxidation process at the same time.

10. The method of claim 9 , wherein an oxygen atomic concentration of the first semiconductor pattern is lower than the oxygen atomic concentration of the first insulating layer.

11. The method of claim 10 , wherein the oxygen atomic concentration of the first semiconductor pattern is substantially equal to the oxygen atomic concentration of the second portion of the semiconductor layer.

12. The method of claim 9 , wherein the first semiconductor pattern injected with the oxygen atoms has a higher electrical conductivity than the first insulating layer.

13. The method of claim 9 , wherein the first semiconductor pattern includes a poly-crystalline semiconductor material, and
wherein the oxygen atoms are injected into a grain boundary of the poly-crystalline semiconductor material of the first semiconductor pattern.

14. The method of claim 9 , further comprising:
forming a lower semiconductor pattern filling a lower region of the through-hole,
wherein the first semiconductor pattern, the second semiconductor pattern, the first insulating pattern and the second insulating pattern are formed in an upper region of the through-hole on the lower semiconductor pattern, and
wherein the first and second semiconductor patterns are defined as an upper semiconductor pattern.

15. The method of claim 9 , further comprising:
patterning the thin layer structure to form a trench that is spaced apart from the through-hole and exposes the substrate;
removing the sacrificial layers exposed by the trench to form recess regions; and
forming gate electrodes in the recess regions, respectively,
wherein the first and second semiconductor patterns include channel regions controlled by the gate electrodes.

Assignees

• Noh Jintae
• Kim Bio
• Shin Su-Jin
• Yang Hanvit
• Hwang Kihyun
• Samsung Electronics Co Ltd

Inventors

• Noh Jintae
• Kim Bio
• Shin Su-Jin
• Yang Hanvit
• Hwang Kihyun

Classifications

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/6519

  the substance being oxygen · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title