Semiconductor devices including gate insulation layers on channel materials and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9997537-B2
Application number	US-201615375387-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Mar 10, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a channel recess in a stack of alternating first insulation layers and sacrificial layers;
forming a first channel material in the channel recess;
forming a charge storage structure on the first channel material, in the channel recess;
forming a second channel material on opposing sidewalls of the charge storage structure, in the channel recess;
removing the sacrificial layers from the stack to expose a sidewall of the first channel material;
oxidizing, via an oxide growth process, the sidewall of the first channel material to form a gate insulation layer, wherein the oxide growth process further comprises growing a second insulation layer on a surface of a substrate to form a sloped interface of the second insulation layer with the substrate; and
forming a gate electrode in a recess adjacent a sidewall of the gate insulation layer, wherein the gate insulation layer is between the first channel material and the gate electrode.

2. The method of claim 1 , wherein oxidizing the sidewall of the first channel material comprises growing the gate insulation layer to protrude into a portion of the recess.

3. The method of claim 2 , wherein the portion of the recess into which the gate insulation layer protrudes comprises a first portion of the recess, and wherein forming the gate electrode comprises forming the gate electrode in a second portion of the recess that is free of the gate insulation layer.

4. The method of claim 3 , wherein forming the gate electrode comprises depositing tungsten adjacent the sidewall of the gate insulation layer, in the second portion of the recess that is free of the gate insulation layer.

5. The method of claim 4 , wherein depositing the tungsten comprises depositing the tungsten on the sidewall of the gate insulation layer, in the second portion of the recess that is free of the gate insulation layer, such that the gate electrode and the gate insulation layer are laterally adjacent and vertically non-overlapping.

6. The method of claim 1 , wherein oxidizing the sidewall of the first channel material comprises converting a portion of the first channel material into an oxide layer while blocking the second channel material from oxidation.

7. The method of claim 1 , further comprising forming a blocking layer pattern in recesses between the first insulation layers, after removing the sacrificial layers.

8. The method of claim 7 , wherein the blocking layer pattern is confined to the recesses.

9. The method of claim 1 , wherein forming the gate electrode comprises forming a gate selection line in the recess adjacent the sidewall of the gate insulation layer, wherein the gate insulation layer is between the first channel material and the gate selection line.

10. The method of claim 9 , wherein:
the recess comprises a first recess;
the gate selection line comprises a first gate selection line; and
forming the gate selection line comprises forming the first gate selection line in the first recess and forming a second gate selection line in a second recess that overlaps the first recess.

11. The method of claim 1 , wherein the first and second channel materials comprise a same semiconductor material.

12. The method of claim 1 , wherein forming the first channel material comprises performing a Selective Epitaxial Growth (SEG) process to form the first channel material in the channel recess, and wherein oxidizing comprises performing the oxide growth process on the sidewall of the first channel material formed by the SEG process to form the gate insulation layer.

13. The method of claim 1 , further comprising forming an opening in the stack after forming the second channel material, wherein removing the sacrificial layers comprises removing the sacrificial layers after forming the opening, and wherein oxidizing via the oxide growth process comprises performing a wet oxidation process via the opening.

14. The method of claim 13 , wherein performing the wet oxidation process comprises forming the gate insulation layer by performing an In Situ Steam Generation (ISSG) process via the opening.

15. The method of claim 13 , wherein:
the method further comprises forming the stack on the substrate; and
forming the opening in the stack comprises exposing the surface of the substrate before growing the second insulation layer.

16. A method of forming a semiconductor device, the method comprising:
forming a plurality of channel recesses in a stack of alternating first insulation layers and sacrificial layers;
forming a first semiconductor channel material in the plurality of channel recesses;
forming charge storage structures in respective ones of the plurality of channel recesses, on the first semiconductor channel material;
forming a second semiconductor channel material on sidewalls of the charge storage structures, in the plurality of channel recesses;
removing the sacrificial layers from the stack to form recesses that expose sidewalls of the first semiconductor channel material;
performing a wet oxidation process on the sidewalls of the first semiconductor channel material to form a gate insulation layer, wherein the wet oxidation process further comprises growing a second insulation layer on a surface of a substrate to form a sloped interface of the second insulation layer with the substrate, and wherein a thickness of a portion of the second insulation layer gradually decreases toward the first semiconductor channel material; and
forming gate electrodes in respective ones of the recesses, wherein the gate insulation layer is between the first semiconductor channel material and the gate electrodes.

17. A method of forming a semiconductor device, the method comprising:
forming a stack of alternating first insulation layers and sacrificial layers on a substrate;
forming a channel recess in the stack to expose a first portion of the substrate;
forming a first channel material on the first portion of the substrate, in the channel recess;
forming a charge storage structure on the first channel material, in the channel recess;
forming a second channel material on opposing sidewalls of the charge storage structure, in the channel recess;
forming an opening in the stack to expose a second portion of the substrate;
removing the sacrificial layers from the stack to expose a sidewall of the first channel material, after forming the opening the stack;
performing a wet oxidation process on the sidewall of the first channel material to form a gate insulation layer, and on the second portion of the substrate to form a second insulation layer, wherein an interface of the second insulation layer with the substrate is curved; and
forming a gate electrode in a recess adjacent a sidewall of the gate insulation layer, wherein the gate insulation layer is between the first channel material and the gate electrode.

18. The method of claim 17 , wherein, after performing the wet oxidation process, a height of an upper surface of the substrate between the channel recess and the opening gradually decreases from the channel recess toward the opening.

19. The method of claim 15 , wherein, after the oxide growth process, a thickness of a portion of the second insulation layer between the channel recess and the opening gradually increases from the channel recess toward the opening.

20. The method of claim 16 , wherein the sloped interface extends to the first semiconductor channel material.

Assignees

• Lee Jung Hwan
• Kim Jee Yong
• Byeon Dae Seok
• Samsung Electronics Co Ltd

Inventors

• Lee Jung-Hwan
• Kim Jee-Yong
• Byeon Dae-Seok

Classifications

• H01L29/66833

  Electricity · mapped topic

• H01L29/42352

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10D64/037

  comprising charge-trapping insulators · CPC title