Die stitching and harvesting of arrayed structures
US-12588494-B2 · Mar 24, 2026 · US
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Zhai Jun patents
Zhai Jun is listed as an inventor on 225 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Zhai Jun |
| Total patents | 225 |
| First publication | Feb 12, 2015 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Structure and method for fabricating a computing system with an integrated voltage regulator module
US-12550412-B2 · Feb 10, 2026 · US
Microelectronic Package RDL Patterns to Reduce Stress in RDLs Across Components
US-2026018527-A1 · Jan 15, 2026 · US
High bandwidth die to die interconnect with package area reduction
US-2026005201-A1 · Jan 1, 2026 · US
Plasma Dicing for Multi-Tier Die for Die Strength Enhancement and Irregular Shaped Dicing
US-2025391664-A1 · Dec 25, 2025 · US
Wafer level integration of passive devices
US-12506117-B2 · Dec 23, 2025 · US
Thermally enhanced chip-on-wafer or wafer-on-wafer bonding
US-12469765-B2 · Nov 11, 2025 · US
Microelectronic package RDL patterns to reduce stress in RDLs across components
US-12456692-B2 · Oct 28, 2025 · US
Direct Wire Reveal Package
US-2025329673-A1 · Oct 23, 2025 · US
Interconnecting a plurality of dies having spare input/output circuit
US-12451436-B2 · Oct 21, 2025 · US
Recent patents
Latest publications not already listed above.
High Bandwidth Memory Buffer Bridge Die in Routing Substrate
US-2025309126-A1 · Oct 2, 2025 · US
Wafer Level Land Grid Array
US-2025300120-A1 · Sep 25, 2025 · US
Unitized Finger to Bump Interposer Package
US-2025253255-A1 · Aug 7, 2025 · US
High bandwidth die to die interconnect with package area reduction
US-12368137-B2 · Jul 22, 2025 · US
Wafer reconstitution and die-stitching
US-12322730-B2 · Jun 3, 2025 · US
Structure and Method for Fabricating a Computing System with an Integrated Voltage Regulator Module
US-2025167048-A1 · May 22, 2025 · US
Wafer Level Integration of Passive Devices
US-2025167176-A1 · May 22, 2025 · US
Systems and methods for interconnecting dies
US-2025157940-A1 · May 15, 2025 · US
Power management system switched capacitor voltage regulator with integrated passive device
US-2025158519-A1 · May 15, 2025 · US
High density interconnection using fanout interposer chiplet
US-2025157939-A1 · May 15, 2025 · US
Wafer reconstitution and die-stitching
US-2025157991-A1 · May 15, 2025 · US
Multi-Die Fine Grain Integrated Voltage Regulation
US-2025149489-A1 · May 8, 2025 · US
High density interconnection using fanout interposer chiplet
US-12283549-B2 · Apr 22, 2025 · US
Power, Signaling and Thermal Path Co-optimization
US-2025112154-A1 · Apr 3, 2025 · US
Structure and method for sealing a silicon IC
US-12261132-B2 · Mar 25, 2025 · US
Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring
US-12249599-B2 · Mar 11, 2025 · US
High Density 3D Interconnect Configuration
US-2025046715-A1 · Feb 6, 2025 · US
Selectable Monolithic or External Scalable Die-to-Die Interconnection System Methodology
US-2025029921-A1 · Jan 23, 2025 · US
Multi-Die Fine Grain Integrated Voltage Regulation
US-2025015033-A1 · Jan 9, 2025 · US
Molding compound layers in semiconductor packages
US-2025014960-A1 · Jan 9, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Apple Inc | 212 |
| Chicago Mercantile Exchange Inc | 12 |
| Chicago Mercantile Exchange | 1 |
| Yee Abraham F | 1 |
| Greco Joe | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/00 | 168 |
| H10W90/724 | 153 |
| H10W70/60 | 127 |
| H10W90/701 | 101 |
| H10W90/722 | 87 |