Die stitching and harvesting of arrayed structures

Patent metadata

Field	Value
Publication number	US-12588494-B2
Application number	US-202318339132-A
Country	US
Kind code	B2
Filing date	Jun 21, 2023
Priority date	Dec 23, 2020
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

First claim

What is claimed is:

1 . A chip structure comprising:
a semiconductor substrate; a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first device area and a first input/output region; a back-end-of-the-line (BEOL) build-up structure spanning over the first device area and the first input/output region; a scribed chip edge adjacent to the first input/output region; wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output region and a terminal end of the die-to-die routing at the scribed chip edge; wherein the semiconductor substrate, the first FEOL die area, and BEOL build-up structure form a first die level; and a second die level hybrid bonded to the first die level, the second die level including a second FEOL die area of a second die patterned into a second semiconductor substrate.

2 . The chip structure of claim 1 , wherein the first input/output region connected to the die-to-die routing is isolated in an off state.

3 . The chip structure of claim 1 , wherein:
the BEOL build-up structure further comprises a first partial metallic seal adjacent to the first input/output region; and the die-to-die routing extends through first openings in the first partial metallic seal.

4 . The chip structure of claim 1 :
further comprising a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area including a second device area and a second input/output region; wherein the first FEOL die area includes a third input/output region; and wherein the BEOL build-up structure spans over the second device area, the second input/output region, and the third input/output region, and the BEOL build-up structure comprises a second die-to-die routing connected between the second input/output region and the third input/output region.

5 . The chip structure of claim 4 , wherein:
the BEOL build-up structure further comprises a second partial metallic seal adjacent to the second input/output region and a third partial metallic seal adjacent to the third input/output region; and the second die-to-die routing extends through second openings in the second partial metallic seal and through third openings in the third partial metallic seal.

6 . A chip structure comprising:
a semiconductor substrate; a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first device area and a first input/output region; a back-end-of-the-line (BEOL) build-up structure spanning over the first device area and the first input/output region; a scribed chip edge adjacent to the first input/output region; wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output region and a terminal end of the die-to-die routing at the scribed chip edge; a second chip hybrid bonded with the BEOL build-up structure; and an encapsulation material laterally surrounding the second chip on the BEOL build-up structure.

7 . The chip structure of claim 6 , further comprising a vertical interconnection extending through the encapsulation material.

8 . The chip structure of claim 7 , further comprising a redistribution layer (RDL) spanning across a side of the encapsulation material opposite the BEOL build-up structure.

9 . The chip structure of claim 8 , further comprising a plurality of solder bumps underneath the RDL.

10 . The chip structure of claim 8 , wherein the second chip comprises a plurality of through silicon vias (TSVs) electrically connected with the RDL.

11 . An electronic structure comprising:
a routing layer; one or more dies on a top side of the routing layer; a plurality of conductive bumps on an underside of the routing layer; and a multi-component device that includes a plurality of co-located components formed in a same substrate, and a terminal side including a plurality of terminals bonded to the underside of the routing layer laterally adjacent to the plurality of conductive bumps, wherein the terminal side of the multi-component device has a non-rectangular area.

12 . The electronic structure of claim 11 , wherein each component of the plurality of co-located components includes separate terminals of the plurality of terminals.

13 . The electronic structure of claim 11 , wherein the plurality of co-located components includes component-to-component routing.

14 . The electronic structure of claim 11 , wherein each component is selected from the group consisting of a capacitor, an inductor, a resistor, and power management integrated circuit.

15 . The electronic structure of claim 11 , wherein the non-rectangular area includes a width area including a first set of terminals of the plurality of terminals connected to a first set of one or more co-located components of the plurality of co-located components, and a length area including a second set of terminals of the plurality of terminals connected to a second set of one or more of co-located components of the plurality of co-located components, wherein the length area and the width area meet at a 90 degree angle.

16 . The electronic structure of claim 15 , wherein the multi-component device is bonded to the underside of the routing layer underneath a circuit block inside one of the one or more dies with an equivalent area as the non-rectangular area of the multi-component device.

17 . The electronic structure of claim 11 , wherein the non-rectangular area matches an area of an intellectual property block within a die of the one or more dies.

18 . The electronic structure of claim 11 , wherein the plurality of co-located components is arranged in a plurality of rows and a plurality of columns, the plurality of rows including a first row and a second row and the plurality of columns including a first column and a second column, wherein the first row includes more co-located components of the plurality of co-located components than the second row, and the first column includes more co-located components of the plurality of co-located components than the second column.

19 . The electronic structure of claim 11 , wherein the plurality of co-located components includes a plurality of power management integrated circuits, and the multi-component device is located underneath a high power consuming circuit block of a die of the one or more dies.

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Zhai Jun
• Hu Kunzhong
• Camenforte Raymundo M

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/732

  between stacked chips · CPC title