High bandwidth die to die interconnect with package area reduction

Patent metadata

Field	Value
Publication number	US-12368137-B2
Application number	US-202318156287-A
Country	US
Kind code	B2
Filing date	Jan 18, 2023
Priority date	Feb 27, 2019
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

First claim

What is claimed is:

1. A package on package structure comprising:
a lower package structure comprising:
a first wiring layer including a first side and a second side;
a first die side-by-side with a vertical interposer including a first side and a second side, wherein the first die and the vertical interposer are on the first side of the first wiring layer;
a second die face down on and electrically connected with the second side of the vertical interposer;
a local interposer on the second side of the first wiring layer underneath and in electrical connection with the first die and the vertical interposer;
a first plurality of conductive pillars laterally adjacent the first die, the vertical interposer, and the second die; and

a top package structure mounted on the lower package structure and in electrical connection with the first plurality of conductive pillars.

2. The package on package structure of claim 1 , wherein the top package structure is mounted onto the first plurality of conductive pillars.

3. The package on package structure of claim 1 , wherein the top package structure includes a single chip.

4. The package on package structure of claim 1 , wherein the top package structure includes a chip connected to a wiring substrate with wire bonds.

5. The package on package structure of claim 1 , further comprising a first molding compound encapsulating the first die, the vertical interposer, and the second die.

6. The package on package structure of claim 5 , further comprising a second molding compound encapsulating the local interposer.

7. The package on package structure of claim 6 , further comprising a second plurality of conductive pillars from the first wiring layer and through the second molding compound.

8. The package on package structure of claim 7 , further comprising a second wiring layer on the second molding compound and connected to the second plurality of conductive pillars.

9. The package on package structure of claim 1 , wherein the second die spans over the first die.

10. The package on package structure of claim 9 , wherein the first die is attached to the second die with an adhesive layer.

11. The package on package structure of claim 1 , wherein the first die occupies a larger area than the second die.

12. The package on package structure of claim 11 , wherein the second die occupies a larger area than both the vertical interposer and the local interposer.

13. The package on package structure of claim 1 , wherein the second die at least partially overlaps the vertical interposer and the first die.

14. The package on package structure of claim 13 , further comprising a mechanical chiplet attached to the first die laterally adjacent to the second die.

15. The package on package structure of claim 1 , wherein the first die comprises a first core selected from the group consisting of a central processing unit and a graphics processing unit.

16. The package on package structure of claim 15 , wherein the second die comprises a memory core.

17. The package on package structure of claim 15 , wherein the second die comprises an RF core.

18. The package on package structure of claim 1 , wherein the first die and the second die comprise split logic.

19. The package on package structure of claim 18 , wherein the top package structure includes a memory chip.

Assignees

• Apple Inc

Inventors

• Zhong Chonghua
• Zhai Jun
• Hu Kunzhong

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title