High density interconnection using fanout interposer chiplet

Patent metadata

Field	Value
Publication number	US-12283549-B2
Application number	US-202318163033-A
Country	US
Kind code	B2
Filing date	Feb 1, 2023
Priority date	Jun 9, 2017
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

First claim

What is claimed is:

1. A package comprising:
an encapsulation layer;
a first component and a second component embedded within the encapsulation layer;
a redistribution layer (RDL) on a first side of the encapsulation layer and directly on and in electrical contact with a first plurality of terminals of the first and second components and a second plurality of terminals of the first component and the second components;
a plurality of conductive pillars extending from a first side of the RDL; and
an interposer chiplet mounted on the first side of the RDL;
wherein the RDL comprises a first area of fan out interconnect routing interconnected with the plurality of conductive pillars, and a second area of routing interconnected with the interposer chiplet, and second area of routing includes an arrangement of stacked vias and underbump metallurgy (UBM) pads on the stacked vias to interconnect the interposer chiplet with the first and second components;
wherein the first plurality of terminals of the first and second components is in electrical connection with the plurality of conductive pillars laterally adjacent the interposer chiplet, and the second plurality of terminals of first and second components is in electrical connection with the arrangement of stacked vias and UBM pads;
wherein the interposer chiplet is bonded directly to the UBM pads of the arrangement of stacked vias and UBM pads of the RDL with a first plurality of first solder bumps.

2. The package of claim 1 , wherein the interposer chiplet interconnects the first and second components.

3. The package of claim 2 , further comprising an underfill material between the interposer chiplet and the encapsulation layer.

4. The package of claim 2 , wherein the interposer chiplet includes interposer routing characterized by a finer pitch than the first area of fan out interconnect routing.

5. The package of claim 2 , wherein the first plurality of terminals has a coarser pitch than the second plurality of terminals.

6. The package of claim 2 , wherein the interposer chiplet includes an integrated passive device.

7. The package of claim 2 , further comprising a second plurality of second solder bumps bonded to the plurality of conductive pillars.

8. The package of claim 2 , wherein the first plurality of first solder bumps is a plurality of micro bumps.

9. The package of claim 2 , wherein the plurality of conductive pillars is not embedded in an encapsulation layer.

10. The package of claim 2 , wherein the interposer chiplet is directly underneath portions of the first component and the second component.

11. The package of claim 2 , further comprising a through via extending though the interposer chiplet.

12. The package of claim 11 , wherein the through via is a through silicon via.

13. The package of claim 11 , further comprising a solder bump on a back side of the interposer chiplet opposite the first plurality of first solder bumps.

14. The package of claim 1 , wherein the first component and the second component each comprises a logic die.

15. The package of claim 1 , wherein the first component comprises a logic die and the second component comprises a memory die.

Assignees

• Apple Inc

Inventors

• Zhai Jun
• Zhong Chonghua
• Hu Kunzhong

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title