Wafer Level Land Grid Array

Patent metadata

Field	Value
Publication number	US-2025300120-A1
Application number	US-202418614332-A
Country	US
Kind code	A1
Filing date	Mar 22, 2024
Priority date	Mar 22, 2024
Publication date	Sep 25, 2025
Grant date	—

Abstract

Packages with wafer level land grid arrays are described. In an embodiment, a package includes a die and a package routing layer over the die, where the package routing layer includes a first land that spans over a first set of vias, and a second land that spans over a second set of vias, where the vias may be connected to a metal redistribution line or directly connected to die contact pad of the die.

First claim

What is claimed is:

1 . A package comprising:
a die; and a package routing layer over the die, wherein the package routing layer includes at least one metal redistribution line, lands, and vias that connect the at least one metal redistribution line to the lands; wherein the lands include at least a first land that spans over a first set of vias, and a second land that spans over a second set of vias.

2 . The package of claim 1 , wherein a first surface area of the first land is different from a second surface area of the second land.

3 . The package of claim 1 , wherein the first set of vias have a first width, and the second set of vias have a second width, the first width being different than the second width.

4 . The package of claim 1 , wherein a first number of vias in the first set of vias is different from a second number of vias in the second set of vias.

5 . The package of claim 1 , wherein the vias include circular, rectangular or oblong vias.

6 . The package of claim 1 , further comprising a voltage converter connected to a third land.

7 . The package of claim 6 , wherein the third land connected to the voltage converter has a surface area greater than a land not connected to the voltage converter.

8 . The package of claim 1 , wherein the lands further include a fourth land, the fourth land being a ground land centrally located to group multiple grounds of the package.

9 . A package comprising:
a die; and a package routing layer over the die, wherein the package routing layer includes lands and vias that that connect directly to the die; wherein the lands include at least a first land that spans over a first set of vias, and a second land that spans over a second set of vias.

10 . The package of claim 9 , wherein a first surface area of the first land is different from a second surface area of the second land.

11 . The package of claim 9 , wherein the first set of vias have a first width, and the second set of vias have a second width, the first width being different than the second width.

12 . The package of claim 9 , wherein a first number of vias in the first set of vias is different from a second number of vias in the second set of vias.

13 . The package of claim 9 , wherein the vias include circular, rectangular or oblong vias.

14 . The package of claim 9 , further comprising a voltage converter connected to a third land.

15 . The package of claim 14 , wherein the third land connected to the voltage converter has a surface area greater than a land not connected to the voltage converter.

16 . The package of claim 9 , wherein the lands further include a fourth land, the fourth land being a ground land centrally located to group multiple grounds of the package.

17 . A system comprising:
a routing structure; a power supply mounted to the routing structure; a first package mounted to the routing structure, the first package including:
a die; and
a package routing layer over the die, wherein the package routing layer includes lands and vias that connect to the die;
wherein the lands include at least a first land that spans over a first set of vias, and a second land that spans over a second set of vias; and
a second package mounted to the routing structure, wherein the first package connects the power supply to the second package.

18 . The system of claim 17 , wherein the routing structure includes at least a first metal trace to connect the power supply to the first package, and a second metal trace to connect the first package to the second package.

19 . The system of claim 17 , wherein the first package is a power management unit.

20 . The system of claim 17 , wherein a first surface area of the first land is different from a second surface area of the second land.

Assignees

• Apple Inc

Inventors

• Camenforte Raymundo M
• Fajardo Raymond
• Carson Flynn P
• Zhai Jun
• Chang Chien-Sheng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/853

  On the same surface · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/237

  Multiple bump connectors having different shapes · CPC title

• H10W72/232

  Plan-view shape, i.e. in top view · CPC title