High Density 3D Interconnect Configuration

Patent metadata

Field	Value
Publication number	US-2025046715-A1
Application number	US-202418923503-A
Country	US
Kind code	A1
Filing date	Oct 22, 2024
Priority date	Feb 5, 2020
Publication date	Feb 6, 2025
Grant date	—

Abstract

Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

First claim

What is claimed is:

1 . An electronic system comprising:
a redistribution layer (RDL); a logic die on a first side of the RDL and a memory device on the first side of the RDL; and a chiplet electrically connected between the logic die and the memory device; wherein the chiplet includes:
plurality of conductive signal lines bridging between the logic die and the memory device; and
a chiplet power delivery network (PDN) between the logic die and the memory device.

2 . The electronic system of claim 1 , wherein the chiplet is embedded in the RDL.

3 . The electronic system of claim 1 , wherein the chiplet is bonded to an underside of the RDL.

4 . The electronic system of claim 1 , wherein the chiplet PDN comprises a negative power supply (Vss) mesh plane.

5 . The electronic system of claim 1 , wherein the chiplet PDN comprises a positive power supply (Vdd) mesh plane.

6 . The electronic system of claim 1 , wherein the chiplet PDN comprises a negative power supply (Vss) mesh plane or a positive power supply (Vdd) mesh plane.

7 . The electronic system of claim 6 , wherein the chiplet is embedded in the RDL.

8 . The electronic system of claim 6 , wherein the chiplet is bonded to an underside of the RDL.

9 . The electronic system of claim 6 , wherein the chiplet comprises a voltage regulator unit connected to the chiplet PDN.

10 . The electronic system of claim 6 , wherein the chiplet comprises a power management unit connected to the chiplet PDN.

11 . The electronic system of claim 6 , wherein the chiplet comprises logic connected to the chiplet PDN.

12 . The electronic system of claim 6 , wherein the chiplet comprises memory connected to the chiplet PDN.

13 . The electronic system of claim 1 , wherein the chiplet comprises a plurality of passive devices connected to the chiplet PDN.

14 . The electronic system of claim 13 , wherein the plurality of passive devices comprises a plurality of capacitors.

15 . The electronic system of claim 1 , wherein the RDL includes coarser pitch routing than the plurality of conductive signal lines.

16 . The electronic system of claim 1 , wherein the RDL further comprises a 3D interconnect structure for Vss and Vdd delivery.

17 . The electronic system of claim 16 , wherein the 3D interconnect structure comprises a power bar directly underneath a plurality of contact pads of the RDL, wherein the plurality of contact pads is coupled with the logic die.

18 . The electronic system of claim 17 , wherein the power bar is electrically coupled with the chiplet PDN.

19 . The electronic system of claim 18 , wherein the chiplet comprises a Vdd mesh plane or the Vss mesh plane.

20 . The electronic system of claim 18 , wherein the chiplet comprises a voltage regulator.

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Cao Zhitao
• Hu Kunzhong
• Zhai Jun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title