Reducing programming disturbance in memory devices
US-2025078940-A1 · Mar 6, 2025 · US
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Yip Aaron patents
Yip Aaron is listed as an inventor on 86 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Yip Aaron |
| Total patents | 86 |
| First publication | Jan 1, 2015 |
| Latest publication | Mar 6, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
3d memory device including shared select gate connections between memory blocks
US-2025037767-A1 · Jan 30, 2025 · US
Memory devices including staircase structures, and related electronic systems
US-2025038109-A1 · Jan 30, 2025 · US
3D memory device including shared select gate connections between memory blocks
US-12131782-B2 · Oct 29, 2024 · US
Devices including stair step structures, and related memory devices and electronic systems
US-12125786-B2 · Oct 22, 2024 · US
Reducing programming disturbance in memory devices
US-12080360-B2 · Sep 3, 2024 · US
Wafer-on-wafer memory device architectures
US-2024062786-A1 · Feb 22, 2024 · US
3d memory device including shared select gate connections between memory blocks
US-2023420049-A1 · Dec 28, 2023 · US
Reducing programming disturbance in memory devices
US-2023360710-A1 · Nov 9, 2023 · US
Reducing programming disturbance in memory devices
US-11688470-B2 · Jun 27, 2023 · US
Recent patents
Latest publications not already listed above.
3D memory device including shared select gate connections between memory blocks
US-11670370-B2 · Jun 6, 2023 · US
Memory device including data lines on multiple device levels
US-11605588-B2 · Mar 14, 2023 · US
Devices including stair step structures, and related memory devices and electronic systems
US-2022384341-A1 · Dec 1, 2022 · US
Reducing programming disturbance in memory devices
US-2022359020-A1 · Nov 10, 2022 · US
Methods of forming memory devices including stair step structures
US-11430734-B2 · Aug 30, 2022 · US
Reducing programming disturbance in memory devices
US-11342034-B2 · May 24, 2022 · US
Memory block select circuitry including voltage bootstrapping control
US-11302397-B2 · Apr 12, 2022 · US
3d memory device including shared select gate connections between memory blocks
US-2022051720-A1 · Feb 17, 2022 · US
3D memory device including shared select gate connections between memory blocks
US-11164629-B2 · Nov 2, 2021 · US
Reducing programming disturbance in memory devices
US-2021287754-A1 · Sep 16, 2021 · US
Memory device including data lines on multiple device levels
US-2021193570-A1 · Jun 24, 2021 · US
Sense flags in a memory device
US-11029861-B2 · Jun 8, 2021 · US
Methods of forming memory devices including stair step structures
US-2021151375-A1 · May 20, 2021 · US
Reducing programming disturbance in memory devices
US-10902927-B2 · Jan 26, 2021 · US
Memory block select circuitry including voltage bootstrapping control
US-2021005262-A1 · Jan 7, 2021 · US
Memory devices including stair step or tiered structures and related methods
US-10879175-B2 · Dec 29, 2020 · US
Microelectronic devices including staircase structures, and related memory devices and electronic systems
US-10847526-B1 · Nov 24, 2020 · US
3d memory device including shared select gate connections between memory blocks
US-2020357468-A1 · Nov 12, 2020 · US
Reducing programming disturbance in memory devices
US-2020321064-A1 · Oct 8, 2020 · US
Memory block select circuitry including voltage bootstrapping control
US-10748620-B2 · Aug 18, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 74 |
| Intel Corp | 9 |
| Yip Aaron | 5 |
| Lodestar Licensing Group Llc | 3 |
| Yu Xiaojun | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/0483 | 53 |
| G11C16/24 | 36 |
| H10B43/50 | 34 |
| G11C16/10 | 28 |
| G11C16/08 | 28 |