Memory block select circuitry including voltage bootstrapping control

Patent metadata

Field	Value
Publication number	US-11302397-B2
Application number	US-202016995361-A
Country	US
Kind code	B2
Filing date	Aug 17, 2020
Priority date	Mar 22, 2018
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

First claim

What is claimed is:

1. An apparatus comprising:
a first memory cell string;
a second memory cell string;
a first group of conductive lines to access the first and second memory cell strings;
a second group of conductive lines;
a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and
a circuit including:
a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node; and
a third transistor including a gate, a first terminal directly coupled to the second node and a second terminal directly coupled to the common gate, wherein the gate of the third transistor is not coupled to the second node.

2. The apparatus of claim 1 , further comprising:
a fourth transistor coupled between the second node and a third node, the fourth transistor including a gate to receive a supply voltage of a memory device that includes the first and second memory cell strings.

3. The apparatus of claim 1 , wherein:
the first node is to receive a first voltage during an operation of storing information in at least one memory cell of the first and second memory cell strings, and the first voltage includes a first value greater than a value of a supply voltage of a memory device that includes the first and second memory cell strings; and
the second group of conductive lines is to receive voltages during the operation, and the first value is no greater than a highest value among values of the voltages received at the second group of conductive lines.

4. An apparatus comprising:
a first memory cell string;
a second memory cell string;
a first group of conductive lines to access the first and second memory cell strings;
a second group of conductive lines;
a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and
a circuit including:
a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node;
a third transistor including a first terminal directly coupled to the second node and a second terminal directly coupled to the common gate;
a fourth transistor coupled between a third node and a fourth node, the fourth transistor including a gate coupled to the common gate; and
a capacitor coupled between the common gate and the fourth node.

5. An apparatus comprising:
a first memory cell string;
a second memory cell string;
a first group of conductive lines to access the first and second memory cell strings;
a second group of conductive lines;
a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and
a circuit including:
a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node; and
a third transistor coupled between the second node and the common gate, wherein:
the first node is to receive a first voltage during an operation of storing information in at least one memory cell among the first and second memory cell strings, and the first voltage includes a first value greater than a value of a supply voltage of a memory device that includes the first and second memory cell strings; and
the third transistor includes a gate coupled to a third node to receive a second voltage during the operation, a terminal to receive an enable signal, and the second voltage includes a second value greater than the value of the supply voltage.

6. The apparatus of claim 5 , wherein the first value is greater than the second value.

7. An apparatus comprising:
a first memory cell string;
a second memory cell string;
a first group of conductive lines to access the first and second memory cell strings;
a second group of conductive lines;
a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and
a circuit including:
a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node;
a third transistor including a first terminal directly coupled to the second node and a second terminal directly coupled to the common gate; and, wherein each of the first and third transistors includes a depletion-mode transistor.

8. An apparatus comprising:
a first memory cell string;
a second memory cell string;
a first group of conductive lines to access the first and second memory cell strings;
a second group of conductive lines;
a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and
a circuit including:
a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor being a depletion mode transistor and including a gate coupled to the second node; and
a third transistor including a first terminal directly coupled to the second node and a second terminal directly coupled to the common gate, the third transistor being a depletion mode transistor; a fourth transistor coupled between the second node and a third node.

9. The apparatus of claim 8 , further comprising:
a fifth transistor coupled between a fourth node and a fifth node, the fifth transistor including a gate coupled to the common gate; and
a capacitor coupled between the common gate and the fourth node.

10. The apparatus of claim 9 , wherein the apparatus comprises a memory device, the first and second memory cell strings are located over a substrate of the memory device, at least a portion of each of the first, second, and third transistors is located in the substrate, and the capacitor is located over the substrate.

11. The apparatus of claim 8 , wherein:
the first node is to receive a first voltage during an operation of storing information in at least one memory cell among the first and second memory cell strings, and the first voltage includes a first value greater than a value of a supply voltage of a memory device that includes the first and second memory cell strings; and
the common gate is configured to have a second voltage during the operation, and the second voltage includes a second value greater than the first value.

12. The apparatus of claim 11 , wherein the third transistor includes a gate to receive a third voltage during the operation, and the third voltage includes a third value less than the first value.

13. The apparatus of claim 11 , wherein the third transistor includes a gate to receive a third voltage during the operation, and the third voltage includes a third value less than the second value.

14. The apparatus of 11 , whe

Assignees

• Micron Technology Inc

Inventors

• Yip Aaron

Classifications

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title