3D memory device including shared select gate connections between memory blocks

Patent metadata

Field	Value
Publication number	US-11670370-B2
Application number	US-202117514899-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Aug 31, 2017
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

First claim

What is claimed is:

1. An apparatus comprising:
a data line;
first, second, third, and fourth memory cell strings coupled to the data line;
a first select line and a first additional select line associated with the first memory cell string;
a second select line and a second additional select line associated with the second memory cell string;
a third select line and a third additional select line associated with the third memory cell string;
a fourth select line and a fourth additional select line associated with the fourth memory cell string;
a first conductive connection coupled to the first and second select lines;
a second conductive connection coupled to the third and fourth select lines;
a third conductive connection coupled to the first additional select line and the third additional select line; and
a fourth conductive connection coupled to the second additional select line and the fourth additional select line.

2. The apparatus of claim 1 , wherein the first, second, third, and fourth select lines have respective lengths in a first direction, and the data line has a length in a second direction.

3. The apparatus of claim 1 , wherein the apparatus comprises a memory device, and the first and third memory cell strings are included in a first block of the memory device, and the second and fourth memory cell strings are included in a second block of the memory device.

4. The apparatus of claim 1 , wherein the apparatus comprises a memory device, and the first and third memory cell strings are included in separate sub-blocks of the memory device, and the second and fourth memory cell strings are included in separate sub-blocks of the memory device.

5. The apparatus of claim 1 , wherein the apparatus comprises a memory device, and the first and third memory cell strings are associated with first word lines of the memory device, and the second and fourth memory cell strings are associated with second word lines of the memory device.

6. The apparatus of claim 1 , wherein the third and fourth conductive connections are electrically separated from each other.

7. An apparatus comprising:
a conductive material;
a first pillar contacting the conductive material;
a second pillar contacting the conductive material;
first memory cells located along the first pillar and between the conductive material and a substrate;
second memory cells located along the second pillar between the conductive material and a substrate;
a first conductive material located in a first level of the apparatus and along the first pillar between the first memory cells and the conductive material;
a second conductive material located in a second level of the apparatus and along the first pillar between the first conductive material and conductive material;
a first additional conductive material located in the first level of the apparatus and along the second pillar between the second memory cells and the conductive material;
a second additional conductive material located in the second level of the apparatus and along the second pillar between the first additional conductive material and the conductive material, wherein the second additional conductive material is electrically separated from the second conductive material; and
a third conductive material coupled to the first conductive material and the first additional conductive material.

8. The apparatus of claim 7 , further comprising:
a first group of conductive materials adjacent the first memory cells and electrically separated from each other; and
a second group of conductive materials adjacent the second memory cells and electrically separated from each other, wherein the first group of conductive materials are located on a same level as the second group of conductive materials.

9. The apparatus of claim 8 , wherein the apparatus comprises a memory device, and the first group of conductive materials are part of first word lines of the memory device, and the second group of conductive materials are part of second word lines of the memory device.

10. The apparatus of claim 7 , wherein the first and second groups of conductive materials are metal.

11. The apparatus of claim 8 , wherein the first and second group of conductive materials are poly silicon.

12. The apparatus of claim 7 , wherein the apparatus comprises a memory device, and the conductive material is part of a bit line of the memory device.

13. The apparatus of claim 12 , wherein first memory cells are included in a first block of the memory device, and the second memory cells are included in a second block of the memory device.

14. The apparatus of claim 13 , wherein the first block is located next to the second block.

15. An apparatus comprising:
a first memory block including:
first memory cell strings;
a first select line associated with a first portion of the first memory strings;
a second select line associated with the first portion of the first memory strings;
a first additional select line associated with a second portion of the first memory cell strings; and

a second additional select line associated with the second portion of the first memory cell strings wherein the second additional select line is electrically coupled to the second select line; and
a second memory block including:
second memory cell strings;
a third select line associated with a first portion of the second memory strings;
a fourth select line associated with the first portion of the second memory strings;
a third additional select line associated with a second portion of the second memory cell strings; and
a fourth additional select line associated with the second portion of the second memory cell strings, wherein the fourth additional select line is coupled to the fourth select line, and wherein:

the first select line is coupled to the third select line; and
the first additional select line is coupled to the third additional select line.

16. The apparatus of claim 15 , wherein the second and fourth select lines are electrically separated from each other.

17. The apparatus of claim 15 , wherein the first select line, the first additional select line, the third select line, and the third additional select line are located on a same level of the apparatus.

18. The apparatus of claim 15 , wherein the second select line, the second additional select line, the fourth select line, and the fourth additional select line are located on a same level of the apparatus.

19. The apparatus of claim 15 , further comprising:
a fifth select line associated with the first and second portions of the first memory cells; and
a sixth select line associated with the first and second portions of the second memory cells.

20. The apparatus of claim 19 , wherein the fifth and sixth select lines are electrically separated from each other.

Assignees

• Micron Technology Inc

Inventors

• Yip Aaron

Classifications

• G11C16/0458

  comprising two or more independent floating gates which store independent data · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title