Memory devices including stair step or tiered structures and related methods

Patent metadata

Field	Value
Publication number	US-10879175-B2
Application number	US-201916405184-A
Country	US
Kind code	B2
Filing date	May 7, 2019
Priority date	Mar 11, 2016
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

First claim

What is claimed is:

1. A three-dimensional (3-D) non-volatile memory device (NAND), comprising:
stair step structures positioned along the memory device, each stair step structure comprising at least two conductive steps, each conductive step of the at least two conductive steps being at least partially separated from an adjacent conductive step of the at least two conductive steps by insulative material;
at least one landing comprising at least one via extending through the memory device, the at least one landing positioned between and separating a first stair step structure of the stair step structures and a second stair step structure of the stair step structures, the first stair step structure and the second stair step structure each being adjacent to the at least one landing on opposing sides of the at least one landing;
access lines, each access line extending from a conductive portion of one conductive step of the at least two conductive steps of the stair step structures to the at least one via; and
at least one control unit positioned proximate at least one of the stair step structures or the at least one landing, the at least one control unit operably coupled to the at least one via.

2. The memory device of claim 1 , wherein the at least one control unit comprises at least one of string driver circuitry, pass gates, circuitry for selecting gates, circuitry for selecting the access lines, circuitry for amplifying signals, or circuitry for sensing signals.

3. The memory device of claim 1 , wherein the at least one control unit comprises pass gates electrically coupled to the access lines for selecting a desired one of the conductive steps.

4. The memory device of claim 1 , wherein at least some of the stair step structures comprise a word line plate structure.

5. The memory device of claim 4 , wherein the word line plate structure is coupled to a word line charge pump.

6. The memory device of claim 4 , wherein the word line plate structure comprises a material including tungsten.

7. The memory device of claim 4 , further comprising a word line driver electrically connected to the word line plate structure.

8. The memory device of claim 1 , wherein one stair step structure of the stair step structures comprises a drain select gate (SGD) structure.

9. The memory device of claim 1 , wherein the at least two conductive steps of each stair step structure comprises a metal material.

10. The memory device of claim 1 , wherein the at least one via comprises a plurality of vias, and wherein each access line extends from a conductive portion of one conductive step of at least two conductive steps of the stair step structures to one via of the plurality of vias.

11. The memory device of claim 1 , further comprising semiconductor pillars extending through at least one of the stair step structures.

12. A memory device, comprising:
tiered structures positioned along the memory device, each tiered structure comprising at least two tiers having a conductive portion, each conductive portion of the at least two tiers being at least partially separated from an adjacent conductive portion of the at least two tiers by insulative material;
a landing comprising vias extending through the memory device at the landing, the landing positioned between a first tiered structure of the tiered structures and a second tiered structure of the tiered structures positioned adjacent to the first tiered structure; and
at least one control unit positioned proximate the landing and coupled to at least one of the vias in the landing.

13. The memory device of claim 12 , further comprising semiconductor pillars extending through the tiered structures and electronically coupled to the conductive portions.

14. The memory device of claim 13 , wherein the conductive portion of the at least two tiers each comprise a word line plate.

15. The memory device of claim 14 , wherein each the word line plate comprises tungsten.

16. The memory device of claim 15 , wherein the at least one control unit comprises a word line driver.

17. The memory device of claim 12 , further comprising stack slot elements extending along the tiered structures.

18. The memory device of claim 17 , wherein the stack slot elements comprise an insulative material positioned over a conductive material deposited in a replacement gate process.

19. A memory device, comprising:
an array of memory cells arranged in pillars;
stair step structures comprising word line plates being in electrical communication with memory cells of the array;
at least one control device for selecting memory cells of the array;
at least one landing comprising vias extending through the at least one landing to the at least one control device, the at least one landing positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures; and
access lines coupled between word line plates of the stair step structures and a first end of the vias, wherein a second end of the vias is electrically coupled to the at least one control device.

Assignees

• Micron Technology Inc

Inventors

• Tessariol Paolo
• Wolstenholme Graham R
• Yip Aaron

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/11548

  Electricity · mapped topic