Reducing programming disturbance in memory devices

Patent metadata

Field	Value
Publication number	US-12080360-B2
Application number	US-202318195181-A
Country	US
Kind code	B2
Filing date	May 9, 2023
Priority date	Oct 8, 2012
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

First claim

What is claimed is:

1. A method, comprising:
programming a memory cell in a block of NAND memory cell strings, the block including multiple sub-blocks of memory cell strings, wherein the memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material;
wherein the programming of a selected NAND memory cell in a selected NAND memory cell string in a selected sub-block, comprises:
during a first interval of a programming operation, precharging channel material of memory cell strings in both the selected sub-block and in at least one unselected sub-block to a precharge voltage, wherein the at least one unselected sub-block does not contain a selected memory cell; and
during a second interval of the programming operation, after the first interval, applying a programming voltage to a first access line coupled to the selected memory cell in the selected sub-block, wherein an unselected memory cell in the at least one unselected sub-block is also coupled to the first access line;
wherein during the second interval of the programming operation, the channel materials of a group of memory cell strings in the unselected sub-block are charged to a first voltage higher than the precharge voltage by a voltage induced on the channel materials of the group of memory cell strings in the unselected sub-block as a result of the programming voltage on the first access line.

2. The method of claim 1 , wherein the multiple memory cell strings within a block collectively form multiple vertically offset levels of memory cells, wherein each level of memory cells in multiple sub-blocks are coupled to a respective common access line.

3. The method of claim 2 , wherein multiple memory cells at a respective level within a block of memory cell strings are coupled to a common access line.

4. The method of claim 1 , wherein the precharging further comprises enabling respective select gates of multiple memory cell strings in the unselected sub-block to couple the precharge voltage to the channel material of the multiple strings of memory cells in the unselected sub-block.

5. The method of claim 4 , wherein the enabled select gates in the unselected sub-block during precharging are the drain select gates of the NAND memory cell strings.

6. The method of claim 4 , wherein the enabled select gates in the unselected sub-block during precharging are the source select gates of the NAND memory cell strings.

7. The method of claim 1 , further comprising allowing the channel material of the strings of memory cells in the unselected sub-block to float during the second interval of the programming operation.

8. The method of claim 7 , wherein allowing the channel material of the string of memory cells in the unselected sub-block to float comprises grounding a select line coupled to a select gate of the string of memory cells in the unselected sub-block.

9. The method of claim 7 , further comprising applying a program enable voltage to a data line during the programming operation, wherein the data line is coupled to strings of memory cells in the unselected sub-block and in the selected sub-block.

10. The method of claim 9 , wherein applying a program enable voltage to a data line of a selected string comprises coupling the data line to a ground potential.

11. The method of claim 10 , further comprising enabling a select gate in the selected string of memory cells to couple the program enable voltage to channel material of the selected memory cell string during the programming operation.

12. A memory structure, comprising:
at least one block of NAND memory including multiple sub-blocks of NAND memory cell strings, wherein the NAND memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material;
a memory device controller, comprising control circuitry configured to perform operations on the memory structure, wherein the operations include programming of a first NAND memory cell in a first NAND memory cell string within a first sub-block, including:
during a first interval of a programming operation, precharging channel material of memory cell strings in both the first sub-block and at least a second sub-block to a precharge voltage, wherein the second sub-block does not contain a selected memory cell; and
during a second interval of the programming operation, after the first interval, applying a programming voltage to a first access line coupled to the first memory cell in the first sub-block, wherein the first access line is further coupled to at least one additional memory cell in the second sub-block;
wherein during the second interval of the programming operation, the channel materials of a group of memory cell strings in the second sub-block are charged to a first voltage higher than the precharge voltage in response to a voltage induced on the channel materials as a result of the programming voltage on the first access line.

13. The memory structure of claim 12 , wherein the first access line is coupled to multiple memory cells in both the first sub-block and the second sub-block.

14. The memory structure of claim 12 , wherein the channel materials of the strings of memory cells in both the first sub-block and the second sub-block are precharged to the precharge voltage during the first interval of the programming operation.

15. The memory structure of claim 14 , wherein the channel material of each NAND memory string includes a semiconductor pillar, and wherein the operations further comprise allowing the pillars of NAND memory cell strings in the second sub-block to float during the second interval of the programming operation.

16. The memory structure of claim 15 , wherein allowing the pillars of the NAND memory cell strings in the second sub-block to float during the second interval of the programming operation comprises placing respective drain select gates of NAND memory cell strings in the second sub-block in a non-conducting state.

17. The memory structure of claim 16 , wherein the operations further comprise, during the second interval of the programing operation, placing the drain select gate of the first memory cell string in a conducting state.

18. A memory device, comprising:
a NAND memory array comprising,
a block of NAND memory cell strings, comprising,
multiple sub-blocks of NAND memory cell strings, each sub-block including multiple strings of NAND memory cells,
wherein strings of NAND memory cells extend between an associated source and an associated data line of multiple data lines, wherein the multiple NAND memory cells in a string are arranged at vertically offset levels along a semiconductor pillar;
a source select gate between the multiple NAND memory cells of the respective string and the source;
a drain select gate between the NAND memory cells and the associated data line; and
multiple access lines coupled to multiple memory cells in a respective vertically offset level, wherein a first access line is coupled to multiple memory cells in at least first and second sub-blocks of the block;
a memory controller, comprising control circuitry configured to perform operations comprising,
performing a programming operation on a selected first memory cell in a first memory cell string in the first sub-block, the programming operation comprising a first portion and a second portion;
during the first portion of the programming operation, precharging the semiconduct

Assignees

• Micron Technology Inc

Inventors

• Yip Aaron

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title