Sense flags in a memory device

Patent metadata

Field	Value
Publication number	US-11029861-B2
Application number	US-201916543743-A
Country	US
Kind code	B2
Filing date	Aug 19, 2019
Priority date	Nov 9, 2010
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells comprising a plurality of pages of memory cells; and
control circuitry for access of the array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising:
reading a first page of memory cells, of the plurality of pages of memory cells, and flag data from a set of flag cells wherein the flag data indicates whether a second page of memory cells, of the plurality of pages of memory cells, adjacent to the first page is programmed; and
determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage.

2. The memory device of claim 1 wherein, in the method that the control circuitry is configured to cause the memory to perform, reading the first page of memory cells and the flag data is performed with one read operation.

3. The memory device of claim 1 wherein the first page of memory cells is an even page, the second page is an odd page, and the flag data indicates whether the odd page is programmed.

4. A memory device, comprising:
a first array of memory cells;
a second array of memory cells; and
control circuitry for access of the first array of memory cells and the second array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising:
performing a sense operation on memory cells of the first array of memory cells coupled to first data lines of the first array of memory cells, and on memory cells of the second array of memory cells coupled to data lines of the second array of memory cells, without performing the sense operation on memory cells of the first array of memory cells coupled to second data lines of the first array of memory cells; and
determining a program indication of the memory cells coupled to the second data lines of the first array of memory cells from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells.

5. The memory device of claim 4 , wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises:
adjusting read gate voltages for a state of the memory cells coupled to the first data lines of the first array of memory cells when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are not programmed.

6. The memory device of claim 4 , wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises:
determining states of the memory cells coupled to the first data lines of the first array of memory cells without adjustment of read gate voltages when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are programmed.

7. The memory device of claim 4 , wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises:
performing a sense operation on a lower page of the memory cells coupled to the first data lines responsive to the program indication.

8. The memory device of claim 4 , wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises:
adjusting read gate voltages for a state of the memory cells coupled to the first data lines of the first array of memory cells when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are programmed.

9. The memory device of claim 4 , wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises:
determining states of the memory cells coupled to the first data lines of the first array of memory cells without adjustment of read gate voltage when the program indication indicates that the memory cells coupled to the second data lines of the first array of memory cells are not programmed.

10. A memory device, comprising:
a first array of memory cells;
a second array of memory cells; and
control circuitry for access of the first array of memory cells and the second array of memory cells, wherein the control circuitry is configured to cause the memory device to perform a method comprising:
programming memory cells coupled to first data lines in the first array of memory cells without programming memory cells coupled to second data lines in the first array of memory cells and without programming memory cells coupled to data lines in the second array of memory cells; and
programming the memory cells coupled to the second data lines in the first array of memory cells while programming the memory cells coupled to the data lines in the second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.

11. The memory device of claim 10 , wherein, in the method that the control circuitry is configured to cause the memory to perform, the method further comprises:
loading user data into a dynamic data cache of the memory device coupled to the first data lines prior to programming the memory cells coupled to the first data lines.

12. The memory device of claim 11 , wherein, in the method that the control circuitry is configured to cause the memory to perform, programming the memory cells coupled to the first data lines in the first array of memory cells comprises programming the memory cells coupled to the first data lines in the first array of memory cells with the user data loaded into the dynamic data cache.

13. The memory device of claim 10 , wherein the flag data comprises a plurality of bytes of data.

14. The memory device of claim 10 , wherein a first data line of the first data lines in the first array of memory cells and a second data line of the second data lines in the first array of memory cells are adjacent first and second data lines.

15. The memory device of claim 14 , wherein, in the method that the control circuitry is configured to cause the memory to perform, a read gate voltage of the memory cell coupled to the first data line of the adjacent first and second data lines is to be adjusted in response to the flag data indicative of the memory cell coupled to the second data line of the adjacent first and second data lines being programmed.

16. A memory device, comprising:
a first array of memory cells;
a second array of memory cells;
a third array of memory cells; and
control circuitry for access of the first array of memory cells, the second array of memory cells and the third array of memory cells, Wherein the control circuitry is configured to cause the memory device to perform a method comprising:
programming memory cells coupled to first data lines in the first array of memory cells comprising loading user data into a dynamic data cache of the memory device coupled to the first data lines prior to programming the memory cells coupled to the first data lines;
programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in the second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed; and
programming memory cells coupled to data lines in the third array of memory cells with other flag data while programming the memory cells coup

Assignees

• Micron Technology Inc

Inventors

• Ahmed Shafqat
• Hasnat Khaled
• Kalavade Pranav
• Parat Krishna
• Yip Aaron
• Helm Mark A
• Bicksler Andrew

Classifications

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G06F3/0665

  at area level, e.g. provisioning of virtual or logical volumes · CPC title

• G06F2212/461

  Sector or disk block · CPC title

• G06F2212/2022

  Flash memory · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title