Reducing programming disturbance in memory devices

Patent metadata

Field	Value
Publication number	US-2025078940-A1
Application number	US-202418794538-A
Country	US
Kind code	A1
Filing date	Aug 5, 2024
Priority date	Oct 8, 2012
Publication date	Mar 6, 2025
Grant date	—

Abstract

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

First claim

1 . (canceled)

2 . A method, comprising:
programming a memory cell in a block of NAND memory cell strings, the block including multiple sub-blocks of NAND memory cell strings, wherein the NAND memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material; wherein the programming comprises:
during a first interval:
applying a first precharging voltage to the respective channel materials of multiple NAND memory cell strings in a first sub-block containing a memory cell for programming and in at least one additional sub-block which does not contain a memory cell selected for programming; and
applying a second voltage to multiple access lines extending across the first sub-block and the at least one additional sub-block, the multiple access lines respectively coupled to multiple respective NAND memory cells in the first sub-block and the additional sub-block, the second voltage causing the NAND memory cells coupled to the access lines to enter a conducting state; and

during a second interval, subsequent to applying the first precharge voltage:
allowing the channel materials of multiple NAND memory cell strings in the at least one additional sub-block to float, and
applying a third programming voltage to multiple NAND memory cells coupled to a first access line, wherein multiple memory cells in the first sub-block and the at least one additional sub-block are also coupled to the first access line;

wherein applying of the third programming voltage to the first access line induces a coupled voltage on the floating channel materials of multiple NAND memory cell strings in the at least one additional sub-block, raising the voltage on the channel materials and inhibiting programming of memory cells in the at least one additional sub-block.

3 . The method of claim 2 , wherein the multiple NAND memory cell strings within a block collectively form multiple vertically offset tiers of NAND memory cells, and wherein access lines within the block of NAND memory strings are coupled to multiple memory cells in a respective tier of NAND memory cells extending across multiple sub-blocks.

4 . The method of claim 2 , wherein allowing the channel material of the multiple NAND memory cell strings in the at least one additional sub-block to float during the second interval comprises grounding a select line coupled to a select gate of the string of memory cells in the at least one additional sub-block.

5 . The method of claim 2 , wherein multiple NAND memory cells in the first sub-block are selected for programming.

6 . The method of claim 5 , further comprising during the second interval, applying a program enable voltage to data lines coupled to strings of NAND memory cells in the first sub-block containing a respective NAND memory cell selected for programming.

7 . The method of claim 5 , wherein applying a program enable voltage to a data line of a NAND memory cell string comprises coupling the data line to a ground potential.

8 . The method of claim 4 , further comprising during the second interval, coupling a program enable voltage to channel material of the NAND memory cell string including the NAND memory cell selected for programming by enabling a select gate of that NAND memory cell string.

9 . A memory structure, comprising:
at least one block of NAND memory including multiple sub-blocks of NAND memory cell strings, wherein the NAND memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material;
a controller configured to cause operations to be performed on the memory structure, wherein the operations include a programming operation, comprising:
during a first interval of the programming operation:
applying a first precharging voltage to respective channel materials of multiple NAND memory cell strings in a first sub-block containing a NAND memory cell selected for programming and in an additional sub-block, which does not contain a memory cell selected for programming; and
applying a second voltage to multiple access lines extending across the first sub-block and the additional sub-block, the multiple access lines respectively coupled to multiple respective NAND memory cells in the first sub-block and the additional sub-block, the second voltage causing channels of the NAND memory cells coupled to the access lines to enter a conducting state; and

during a second interval of the programming operation, subsequent to applying the first precharge voltage:
allowing the channel materials of NAND memory cell strings in the additional sub-block to float, and
applying a third programming voltage to multiple NAND memory cells coupled to a first access line, wherein multiple memory cells in the first sub-block and the at least one additional sub-block are also coupled to the first access line;

wherein applying of the third programming voltage to the first access line induces a coupled voltage on the floating channel materials of the multiple NAND memory cell strings in the additional sub-block, raising the voltage on the channel materials and inhibiting programming of memory cells in the additional sub-block.

10 . The memory structure of claim 9 , wherein the multiple NAND memory cell strings within a block collectively form multiple vertically offset levels of NAND memory cells, and wherein access lines within the block of NAND memory strings are coupled to multiple memory cells in a respective level of NAND memory cells extending across multiple sub-blocks.

11 . The memory structure of claim 9 , wherein allowing the channel material of the multiple NAND memory cell strings in the additional sub-block to float during the second interval comprises grounding a select line coupled to a select gate of the string of NAND memory cells in the additional sub-block.

12 . The memory structure of claim 9 , further comprising, during the second interval of the programming operation, reducing voltage on the channel material of the NAND memory cell string containing the selected memory cell to a program enable voltage lower than the precharge voltage.

13 . The memory structure of claim 9 , further comprising during the second interval of the programming operation, applying a program enable voltage to data lines coupled to strings of NAND memory cells in the first sub-block containing a respective NAND memory cell selected for programming.

14 . The memory structure of claim 13 , wherein applying a program enable voltage to a data line of a NAND memory cell string comprises coupling the data line to a ground potential.

15 . The memory structure of claim 9 , further comprising during the second interval of the programming operation, coupling a program enable voltage to channel material of the NAND memory cell string including the NAND memory cell selected for programming by enabling a select gate of that NAND memory cell string.

16 . A memory structure, comprising:
a block of NAND memory including multiple sub-blocks of NAND memory cell strings, each NAND memory cell string respectively including multiple NAND memory cells sharing a common channel material, and further including a source select gate and a drain select gate at opposite sides of the multiple NAND memory cells of the string;
wherein the memory cells of each memory cell string are coupled to respective access lines;
wherein each access line is coupled to memory cells in at least two sub-blocks of the block of NAND memory; and
wher

Assignees

• Micron Technology Inc

Inventors

• Yip Aaron

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title