Methods and apparatus to reduce retimer latency and jitter
US-12580720-B2 · Mar 17, 2026 · US
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Xavier Ani patents
Xavier Ani is listed as an inventor on 31 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Xavier Ani |
| Total patents | 31 |
| First publication | Oct 19, 2017 |
| Latest publication | Mar 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Feed forward equalizers with current mode sampling
US-12568004-B2 · Mar 3, 2026 · US
Retimer with slicer level adjustment
US-12542556-B2 · Feb 3, 2026 · US
Pre-tap equalizable continuous time linear equalizer
US-2025365180-A1 · Nov 27, 2025 · US
Feed forward equalizers with current mode sampling
US-2025260604-A1 · Aug 14, 2025 · US
Pretap equalizable continuous time linear equalizer
US-12388688-B2 · Aug 12, 2025 · US
Pretap equalizable continuous time linear equalizer
US-2025184190-A1 · Jun 5, 2025 · US
Methods and apparatus to reduce retimer latency and jitter
US-2024259175-A1 · Aug 1, 2024 · US
Methods and apparatus to reduce retimer latency and jitter
US-11956340-B1 · Apr 9, 2024 · US
Methods and apparatus to reduce retimer latency and jitter
US-2024113851-A1 · Apr 4, 2024 · US
Recent patents
Latest publications not already listed above.
Retimer with slicer level adjustment
US-2024030926-A1 · Jan 25, 2024 · US
Signal transmission system for use with eye diagram monitor
US-11855816-B2 · Dec 26, 2023 · US
Charge pump with output current adjustment
US-11722142-B1 · Aug 8, 2023 · US
Signal transmission system for use with eye diagram monitor
US-2023054834-A1 · Feb 23, 2023 · US
Offset correction in high-speed serial link receivers
US-11469928-B2 · Oct 11, 2022 · US
Calibration of skew between clock phases
US-11416021-B2 · Aug 16, 2022 · US
Calibration of skew between clock phases
US-2022197330-A1 · Jun 23, 2022 · US
Offset Correction in High-Speed Serial Link Receivers
US-2022182266-A1 · Jun 9, 2022 · US
Serial receiver equalization circuit
US-11063793-B1 · Jul 13, 2021 · US
Negative capacitance circuits including temperature-compensation biasings
US-2019363679-A1 · Nov 28, 2019 · US
Top plate sampling circuit including input-dependent dual clock boost circuits
US-10439628-B2 · Oct 8, 2019 · US
Negative capacitance circuits including temperature-compensation biasings
US-10425042-B2 · Sep 24, 2019 · US
Parasitic capacitance cancellation using dummy transistors
US-10396766-B2 · Aug 27, 2019 · US
Negative capacitance circuits including temperature-compensation biasings
US-2019207564-A1 · Jul 4, 2019 · US
Top Plate Sampling Circuit Including Input-Dependent Dual Clock Boost Circuits
US-2019207617-A1 · Jul 4, 2019 · US
Parasitic capacitance cancellation using dummy transistors
US-2019199332-A1 · Jun 27, 2019 · US
Pattern based estimation of errors in ADC
US-10320405-B2 · Jun 11, 2019 · US
Top plate sampling circuit including input-dependent dual clock boost circuits
US-10084466-B1 · Sep 25, 2018 · US
Pattern based estimation of errors in adc
US-2018191362-A1 · Jul 5, 2018 · US
Pattern based estimation of errors in ADC
US-9941893-B2 · Apr 10, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Texas Instruments Inc | 31 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04L25/03885 | 7 |
| H04L25/4917 | 7 |
| H04L25/03057 | 6 |
| H04L27/01 | 6 |
| H04L25/03878 | 5 |