Charge pump with output current adjustment

Patent metadata

Field	Value
Publication number	US-11722142-B1
Application number	US-202217849594-A
Country	US
Kind code	B1
Filing date	Jun 25, 2022
Priority date	Jun 25, 2022
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

In described examples, a charge pump includes an output, first and second transistors, a control circuit, a multiplexer, and a calibration circuit. The first transistor's drain is coupled to the output. The second transistor's drain is part of a current path separate from a current path that includes the first transistor's drain. The control circuit generates a control signal in response to voltages at the gates of the first and second transistors. First and second inputs of the multiplexer are respectively coupled to sources of the first and second transistors. A control input of the multiplexer is coupled to receive the control signal. A first input of the calibration circuit is coupled to an output of the multiplexer. A second input of the calibration circuit receives a reference voltage. First and second outputs of the calibration circuit are respectively coupled to body terminals of the first and second transistors.

First claim

What is claimed is:

1. A charge pump, comprising:
an output terminal;
a first transistor including a source, a drain, a gate, and a body terminal, the drain of the first transistor coupled to the output terminal;
a second transistor including a source, a drain, a gate, and a body terminal, the drain part of a current path that is separate from a current path that includes the drain of the first transistor;
a control circuit including an output, the control circuit configured to generate a first control signal in response to a voltage at the gate of the first transistor and a voltage at the gate of the second transistor;
a multiplexer (MUX) including a first input, a second input, a control input, and an output, the first input of the MUX coupled to the source of the first transistor and the second input of the MUX coupled to the source of the second transistor, the control input of the MUX coupled to the output of the control circuit;
a reference voltage terminal adapted to receive a reference voltage; and
a calibration circuit including a first input, a second input, a first output and a second output, the first input of the calibration circuit coupled to the output of the MUX, the second input of the calibration circuit coupled to the reference voltage terminal, the first output of the calibration circuit coupled to the body terminal of the first transistor, and the second output of the calibration circuit coupled to the body terminal of the second transistor.

2. The charge pump of claim 1 , wherein the calibration circuit is configured to modify a body-source voltage of a one of the first transistor and the second transistor corresponding to the control input of the MUX in response to a difference between the reference voltage and a voltage at the source of the one of the first transistor and the second transistor corresponding to the control input of the MUX.

3. The charge pump of claim 1 , wherein the calibration circuit includes a comparator having a first input, a second input, and an output, the first input of the comparator coupled to the first input of the calibration circuit, the second input of the comparator coupled to the second input of the calibration circuit.

4. The charge pump of claim 3 , wherein the calibration circuit includes:
a memory including an input, a first output, and a second output, the input of the memory coupled to the output of the comparator; and
a voltage generator including first and second inputs and first and second outputs, the first and second inputs of the generator respectively coupled to the first and second outputs of the memory, the first and second outputs of the generator respectively coupled to the first and second outputs of the calibration circuit.

5. The charge pump of claim 4 ,
wherein the memory is configured to adjust a level of a second control signal in response to the first input of the memory, to adjust a level of a third control signal in response to the second input of the memory, and to continuously provide the second and third control signals respectively to the first and second outputs of the memory; and
wherein the voltage generator is configured to generate first and second body signals with voltages respectively responsive to the first and second inputs of the generator.

6. The charge pump of claim 3 , wherein the calibration circuit includes:
a memory including first and second inputs and first and second outputs, the first input of the memory coupled to the output of the comparator, the second input of the memory coupled to the output of the control circuit, the memory configured to adjust a level of a second control signal or a third control signal in response to the first and second inputs of the memory, and to continuously output the second and third control signals; and
a voltage generator including first and second generator inputs and first and second generator outputs, the first and second generator inputs respectively coupled to the first and second memory outputs, the first and second generator outputs respectively coupled to the first and second calibration outputs, the voltage generator configured to generate first and second body signals with voltages respectively responsive to the first and second inputs of the generator, and to provide the first and second body signals respectively to the first and second outputs of the generator.

7. The charge pump of claim 1 , further including:
a third transistor including a source, a drain, a gate, and a body terminal, the source of the third transistor coupled to the source of the first transistor and the first input of the MUX, the drain of the third transistor coupled to the drain of the second transistor;
a fourth transistor including a source, a drain, a gate, and a body terminal, the source of the fourth transistor coupled to the source of the second transistor and the second input of the MUX, the drain of the fourth transistor coupled to the drain of the first transistor and the output terminal;
wherein the control circuit is configured to generate the first control signal in response to a voltage at the gate of the third transistor and a voltage at the gate of the fourth transistor; and
wherein the calibration circuit includes third and fourth calibration outputs, the third calibration output coupled to the third body terminal, the fourth calibration output coupled to the fourth body terminal.

8. The charge pump of claim 7 , further including first, second, and third current sources, the first current source coupled to the drains of the first and third transistors and the output terminal, the second current source coupled to the sources of the first and fourth transistors, the third current source coupled to the sources of the second and third transistors.

9. The charge pump of claim 7 ,
further including an error amplifier including a non-inverting input, an inverting input, and an output;
wherein the non-inverting input of the error amplifier is coupled to the output terminal and to the drains of the first and third transistors; and
wherein the inverting input of the amplifier is coupled to the output of the amplifier and to the drains of the second and fourth transistors.

10. The charge pump of claim 9 , wherein the calibration circuit includes a comparator having a first input, a second input, and an output, the first input of the comparator coupled to the first input of the calibration circuit, the second input of the comparator coupled to the second input of the calibration circuit.

11. The charge pump of claim 10 , wherein the calibration circuit includes:
a memory including first and second inputs, and first, second, third, and fourth outputs, the first input of the memory coupled to the output of the comparator, the second input of the memory coupled to the output of the control circuit; and
a voltage generator including first, second, third, and fourth inputs and first, second, third, and fourth outputs, the first, second, third, and fourth inputs of the voltage generator respectively coupled to the first, second, third, and fourth outputs of the memory, the first, second, third, and fourth outputs of the voltage generator respectively coupled to the first, second, third, and fourth outputs of the calibration circuit.

12. The charge pump of claim 11 ,
wherein the memory is configured to increment or decrement a level of a first, second, third, or fourth generator control signal in response to the memory accumulator input and the memory control input, and to continuously output the first, second, third, and fourth generator control signals; and
wherein the generator is configured to generate first, second, third, and fo

Assignees

• Texas Instruments Inc

Inventors

• Venkataraman Jagannathan
• Xavier Ani
• Subramanian Shyam

Classifications

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title