Pretap equalizable continuous time linear equalizer

Patent metadata

Field	Value
Publication number	US-12388688-B2
Application number	US-202318524463-A
Country	US
Kind code	B2
Filing date	Nov 30, 2023
Priority date	Nov 30, 2023
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A circuit includes first, second, third, and fourth transistors, and a capacitor. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal, second terminal, and a control terminal. The capacitor has a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor. The third transistor has a first terminal coupled to the first terminal of the second transistor, a second terminal, and a control terminal coupled to the control terminal of the first transistor. The fourth transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the third transistor, and a control terminal coupled to the control terminal of the second transistor.

First claim

What is claimed is:

1. A circuit comprising:
a first transistor having a first terminal, a second terminal, and a control terminal;
a second transistor having a first terminal, second terminal, and a control terminal;
a capacitor having a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor;
a third transistor having:
a first terminal coupled to the first terminal of the second transistor;
a second terminal; and
a control terminal coupled to the control terminal of the first transistor; and

a fourth transistor having:
a first terminal coupled to the first terminal of the first transistor;
a second terminal coupled to the second terminal of the third transistor; and
a control terminal coupled to the control terminal of the second transistor.

2. The circuit of claim 1 , further comprising:
a fifth transistor having:
a first terminal coupled to the second terminal of the fourth transistor;
a second terminal; and
a control terminal coupled to a pre-tap equalization enable terminal; and

a current source having:
a first terminal coupled to the second terminal of the fifth transistor; and
a second terminal coupled to a reference voltage terminal.

3. The circuit of claim 1 , further comprising:
a resistor having:
a first terminal coupled to the second terminal of the first transistor; and
a second terminal coupled to the second terminal of the second transistor;

a first current source having:
a first terminal coupled to the second terminal of the first transistor; and
a second terminal coupled to a reference voltage terminal; and

a second current source having:
a first terminal coupled to the second terminal of the second transistor; and
a second terminal coupled to a reference voltage terminal.

4. The circuit of claim 1 , further comprising:
a fifth transistor having a first terminal, a second terminal, and a control terminal the control terminal coupled to a pre-tap equalization disable terminal;
a first resistor having:
a first terminal coupled to the second terminal of the first transistor; and
a second terminal coupled to the first terminal of the fifth transistor;

a second resistor having:
a first terminal; and coupled to the second terminal of the fifth transistor; and
a second terminal coupled to the second terminal of the second transistor;

a first current source having:
a first terminal coupled to the second terminal of the first transistor; and
a second terminal coupled to a reference voltage terminal; and

a second current source having:
a first terminal coupled to the second terminal of the second transistor; and
a second terminal coupled to the reference voltage terminal.

5. The circuit of claim 3 , further comprising:
a fifth transistor having:
a first terminal;
a second terminal coupled to first terminal of the second current source; and
a control terminal coupled to the second terminal of the first transistor;

a sixth transistor having:
a first terminal coupled to the first terminal of the fifth transistor;
a second terminal coupled to the first terminal of the first current source; and
a control terminal coupled to the second terminal of the second transistor; and

a third current source having:
a first terminal coupled to a power supply terminal; and
a second terminal coupled to the first terminal of the fifth transistor.

6. The circuit of claim 1 , further comprising:
a fifth transistor having:
a first terminal coupled to the first terminal of the second transistor;
a second terminal coupled to the first terminal of the third transistor; and
a control terminal;

a sixth transistor having:
a first terminal coupled to the first terminal of the first transistor;
a second terminal coupled to the first terminal of the fourth transistor; and
a control terminal coupled to the control terminal of the fifth transistor;

a seventh transistor having:
a first terminal coupled to the first terminal of the sixth transistor;
a second terminal coupled to the second terminal of the fifth transistor; and
a control terminal;

an eighth transistor having:
a first terminal coupled to the first terminal of the fifth transistor;
a second terminal coupled to the second terminal of the sixth transistor; and
a control terminal coupled to the control terminal of the seventh transistor.

7. A circuit comprising:
a first transistor having a first terminal, a second terminal, and a control terminal;
a second transistor coupled to the first transistor as a first differential pair, the second transistor having a first terminal, a second terminal, and a control terminal;
a third transistor having:
a first terminal coupled to the first terminal of the second transistor;
a second terminal; and
a control terminal coupled to the control terminal of the first transistor;

a fourth transistor coupled to the third transistor as a second differential pair, the fourth transistor having:
a first terminal coupled to the first terminal of the first transistor;
a second terminal; and
a control terminal coupled to the control terminal of the second transistor; and

a fifth transistor coupled to the second differential pair, the fifth transistor configured to switchably enable pre-tap equalization.

8. The circuit of claim 7 , further comprising:
a current source having:
a first terminal; and
a second terminal coupled to a reference voltage terminal;

wherein:
the fifth transistor has:
a first terminal coupled to the second terminal of the third transistor and the second terminal of the fourth transistor;
a second terminal coupled to the first terminal of the current source; and
a control terminal coupled to a pre-tap equalization enable terminal.

9. The circuit of claim 7 , further comprising:
a sixth transistor having:
a first terminal coupled to the first terminal of the first transistor;
a second terminal coupled to the first terminal of the fourth transistor; and
a control terminal;

a seventh transistor having:
a first terminal coupled to the first terminal of the sixth transistor;
a second terminal coupled to the first terminal of the third transistor; and
a control terminal;

an eighth transistor having:
a first terminal coupled to the first terminal of the second transistor;
a second terminal coupled to the second terminal of the sixth transistor; and
a control terminal coupled to the control terminal of the seventh transistor;

wherein the fifth transistor has:
a first terminal coupled to the first terminal of the second transistor;
a second terminal coupled to the first terminal of the third transistor; and
a control terminal coupled to the control terminal of the sixth transistor.

10. The circuit of claim 7 , further comprising a capacitor having:
a first conductor coupled to the second terminal of the first transistor; and
a second conductor coupled to the second terminal of the second transistor.

11. The circuit of claim 10 , further comprising:
a first current source having:
a first terminal coupled to the first conductor;
a second terminal coupled to a reference voltage terminal; and

a second current source having:
a first terminal coupled to the second conductor; and
a second terminal coupled to the reference voltage terminal.

12. The circuit of claim 7 , further comprising a resistor having:
a first terminal coupled to the second terminal of the first transistor; and
a second terminal coupled to the second terminal of the second transistor.

13. The circuit of cla

Assignees

• Texas Instruments Inc

Inventors

• Venkataraman Jagannathan
• Xavier Ani
• Mohan Arun

Classifications

• H04L27/01

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04L5/0005

  Time-frequency · CPC title

• H04L1/0041

  Arrangements at the transmitter end · CPC title

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H04L25/0292 Primary

  Arrangements specific to the receiver end · CPC title