Pattern based estimation of errors in ADC

Patent metadata

Field	Value
Publication number	US-10320405-B2
Application number	US-201815909378-A
Country	US
Kind code	B2
Filing date	Mar 1, 2018
Priority date	Apr 19, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

First claim

What is claimed is:

1. An analog to digital converter (ADC) comprising:
a flash ADC configured to generate a flash output in response to an input signal;
an error correction block configured to generate a known pattern; and
a residual ADC configured to generate a residual code in response to the input signal, the known pattern and an analog PRBS (pseudo random binary sequence)signal.

2. The ADC of claim 1 further comprising:
a selector block coupled to the flash ADC and the error correction block, and configured to generate a plurality of selected signals in response to the flash output and the known pattern;
a digital to analog converter (DAC) coupled to the selector block, and configured to generate a coarse analog signal in response to the plurality of selected signals; and
a residue amplifier coupled to the DAC, and configured to generate a residual analog signal in response to the coarse analog signal, the input signal and the analog PRBS signal, wherein the residual ADC is coupled to the residue amplifier.

3. The ADC of claim 1 further comprising:
a secondary multiplexer coupled to the error correction block and configured to generate a digital PRBS signal in response to the known pattern, a coarse PRBS signal and a secondary control signal, wherein the error correction block is configured to provide the coarse PRBS signal and the secondary control signal to the secondary multiplexer; and
a secondary DAC element coupled to the secondary multiplexer, and configured to generate the analog PRBS signal in response to the digital PRBS signal.

4. The ADC of claim 1 , wherein the residual code is averaged over T cycles to measure an averaged code generated by the ADC, where T is an integer.

5. The ADC of claim 2 , wherein:
the selector block is configured to receive a plurality of control signals from the error correction block; and
the error correction block is configured to receive the flash output and the residual code.

6. The ADC of claim 2 , wherein:
the selector comprises a plurality of primary multiplexers, and each primary multiplexer is configured to generate a selected signal of the plurality of selected signals in response to the known pattern, the flash output and a control signal of the plurality of control signals; and
the DAC comprises a plurality of primary DAC elements, and each of the primary DAC element is configured to receive the selected signal.

7. The ADC of claim 1 , wherein the ADC is configured to operate in a startup mode and a steady-state mode, wherein in the startup mode the error correction block is configured to measure a coarse gain error, a fine gain error, a PRBS error, a memory error and a DAC mismatch error, and the error correction block is configured to generate a corrected PRBS design value based on the coarse gain error, the fine gain error, the PRBS error, the memory error and the DAC mismatch error, and wherein the error correction block is configured to use the corrected PRBS design value in the steady-state mode to measure the input signal.

8. The ADC of claim 7 , wherein the error correction block is configured to provide the known pattern to a primary DAC element of the plurality of primary DAC elements, and the flash ADC is configured to provide a predefined set of bits to the remaining primary DAC elements.

9. The ADC of claim 8 , wherein the error correction block is configured to measure the coarse gain error from the averaged code generated by the ADC, a step size of the DAC and a reference averaged code.

10. The ADC of claim 7 , wherein the error correction block is configured to provide the known pattern to each primary DAC element over M loops, where M is an integer and M is equal to a number of primary DAC elements, and in each loop of M loops:
the error correction block configured to provide the known pattern to a primary DAC element of the plurality of primary DAC elements;
the flash ADC configured to provide the predefined set of bits to the remaining primary DAC elements; and
the error correction block configured to measure the averaged code generated by the ADC.

11. The ADC of claim 10 , wherein the error correction block is configured to measure the fine gain error from the averaged code generated by the ADC in each loop of the M loops, the step size of the DAC and the reference averaged code.

12. The ADC of claim 11 , wherein the error correction block is configured to measure a mismatch of a first primary DAC element of the plurality of primary DAC elements from the coarse gain error, the fine gain error, the step size of the DAC and the averaged code generated by the ADC in a first loop of M loops, wherein the known pattern is provided to the first DAC element in the first loop.

13. The ADC of claim 7 , wherein the error correction block is configured to provide the known pattern to the secondary multiplexer, and the digital PRBS signal is equal to known pattern, and the error correction block is configured to measure the averaged code generated by the ADC.

14. The ADC of claim 13 , wherein the error correction block is configured to measure the PRBS error from the averaged code generated by the ADC, the fine gain error, the coarse gain error, the reference averaged code and a magnitude of the coarse PRBS signal.

15. The ADC of claim 7 , wherein the error correction block is configured to provide the known pattern to a primary DAC element of the plurality of primary DAC elements, and the flash ADC is configured to provide the predefined set of bits to the remaining primary DAC elements, and the error correction block is configured to measure a sub-averaged code generated by the ADC, the sub-averaged code is average of the residual code generated when consecutive bits in the known pattern undergo a state transition over T cycles.

16. The ADC of claim 15 , wherein the error correction block is configured to measure the memory error from the sub-averaged code generated by the ADC, the step size of the DAC, the coarse gain error, the fine gain error and the reference averaged code.

17. A method of converting an input signal in an analog to digital converter (ADC) comprising:
generating a flash output in response to the input signal;
generating a known pattern by an error correction block;
generating a residual code in response to the input signal, the known pattern and an analog PRBS (pseudo random binary sequence) signal; and
averaging the residual code over T cycles to generate an averaged code, where T is an integer.

18. The method of claim 17 further comprising:
generating a plurality of selected signals in response to the flash output and the known pattern;
generating a coarse analog signal by a digital to analog converter (DAC) in response to the plurality of selected signals;
generating a residual analog signal in response to the coarse analog signal, the input signal and the analog PRBS signal;
multiplexing the known pattern and a coarse PRBS signal to generate a digital PRBS signal; and
generating the analog PRBS signal in response to the digital PRBS signal.

19. The method of claim 17 , wherein the DAC comprises a plurality of primary DAC elements, and each of the primary DAC element is configured to receive a selected signal of the plurality of selected signals.

20. The method of claim 17 further comprising operating the ADC in a startup mode and a steady-state mode, wherein the startup mode comprises:
measuring a coarse gain error, a fine gain error, a PRBS error, a memory error and a DAC mismatch error; and
gen

Assignees

• Texas Instruments Inc

Inventors

• Reddy Naru Srinivas Kumar
• Appala Visvesvaraya Pentakota
• Dusad Shagun
• Shrivastava Neeraj
• Nagarajan Viswanathan
• Xavier Ani
• Soundararajan Rishi
• Nurani Sai Aditya
• Francis Roswald

Classifications

• H03M1/109

  for DC performance, i.e. static testing (H03M1/1085 takes precedence) · CPC title

• H03M1/1205

  Multiplexed conversion systems · CPC title

• H03M1/1038 Primary

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/06 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title