Methods and apparatus to reduce retimer latency and jitter

Patent metadata

Field	Value
Publication number	US-12580720-B2
Application number	US-202418629247-A
Country	US
Kind code	B2
Filing date	Apr 8, 2024
Priority date	Sep 29, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.

First claim

What is claimed is:

1 . An apparatus comprising:
a received data input; a data output; clock generation circuitry having a transmission clock output and configured to generate a plurality of receiver clocks at a corresponding one of a plurality of receiver clock outputs, each of the plurality of receiver clocks having a different phase shift; interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including:
comparison circuitry coupled to the clock generation circuitry;
clock configuration circuitry coupled to the comparison circuitry; and
a plurality of flip-flops coupled to the clock configuration.

2 . The apparatus of claim 1 , wherein the clock generation circuitry includes:
clock gate and reset circuitry having a gated clock output; a current mode logic (CML) driver coupled to the gated clock output and having a CML clock signal at a CML output; a CML to complementary metal-oxide semiconductor (CMOS) converter coupled to the CML output and having a transmission clock output; and a clock divider coupled to the transmission clock output.

3 . The apparatus of claim 2 , wherein the clock gate and reset circuitry generates a clock gate enable signal to deterministically set a latency of the transmission clock.

4 . The apparatus of claim 1 , wherein the handoff circuitry is first handoff circuitry, the apparatus further including second handoff circuitry including:
deserializer circuitry coupled to the plurality of data outputs and having a plurality of receiver data stream outputs; a buffer coupled to each of the plurality of receiver data stream outputs and having a plurality of buffered data stream outputs; and serializer circuitry coupled to each of the plurality of buffered data stream outputs.

5 . The apparatus of claim 1 , wherein the comparison circuitry generates a data output signal, the data output signal to determine a phase handoff between the transmission clock and a zero degrees phase shift included in the plurality of receiver clocks.

6 . The apparatus of claim 1 , wherein the clock configuration circuitry is a finite state machine (FSM) that couples one of the plurality of receiver clock outputs to the plurality of flip-flops based on the comparison circuitry.

7 . The apparatus of claim 6 , wherein the FSM configures the plurality of flip-flops to latch the plurality of data outputs at a first time based on the comparison of the plurality of receiver clocks to the transmission clock and a second time based on the transmission clock to generate the plurality of transmission data streams.

8 . A device comprising:
clock generation circuitry; interleaving circuitry coupled to the clock generation circuitry; first handoff circuitry coupled to the clock generation circuitry and the interleaving circuitry; second handoff circuitry coupled to the clock generation circuitry and the interleaving circuitry; and serializer circuitry selectively coupled to the first handoff circuitry and the second handoff circuitry.

9 . The device of claim 8 , wherein the clock generation circuitry includes:
clock gate and reset circuitry coupled to the first handoff circuitry; a current mode logic (CML) driver coupled to the clock gate and reset circuitry; a CML to complementary metal-oxide semiconductor (CMOS) converter coupled to the clock gate and reset circuitry; and a clock divider coupled to first handoff circuitry, the second handoff circuitry, the serializer circuitry, and the CML to CMOS converter.

10 . The device of claim 9 , wherein the clock gate and reset circuitry generates a clock gate enable signal to deterministically set a latency of the transmission clock.

11 . The device of claim 8 , wherein serializer circuitry is a first serializer circuitry, the first handoff circuitry further including:
deserializer circuitry coupled to the interleaving circuitry and the clock generation circuitry; the buffer coupled to the deserializer circuitry; and second serializer circuitry coupled to the clock generation circuitry, the first serializer circuitry, and the buffer.

12 . The device of claim 11 , wherein the buffer is a first in first out (FIFO) buffer.

13 . The device of claim 8 , wherein the second handoff circuitry includes:
comparison circuitry coupled to the clock generation circuitry; a finite state machine (FSM) coupled to the comparison circuitry; and a plurality of flip-flops coupled to the clock generation circuitry and the interleaving circuitry.

14 . The device of claim 13 , wherein the comparison circuitry generates an output to determine a phase handoff between a transmission clock and a zero degrees phase shift included in a plurality of receiver clocks.

15 . The device of claim 14 , wherein the FSM configures the plurality of flip-flops to latch receiver data streams at a first time based on the comparison of a plurality of receiver clocks to the transmission clock and a second time based on the transmission clock to generate a plurality of transmission data streams.

16 . A method comprising:
interleaving a receiver input based on receiver clock signals of different phases to generate a plurality of receiver data streams; comparing the receiver clock signals to a transmission clock; selecting a phase shift handoff based on the comparison; configuring multiplexer circuitry to latch the plurality of receiver data streams based on the phase shift handoff; latching the plurality of receiver data streams based on a first clock corresponding to the phase shift handoff to generate latched receiver data streams; latching the latched receiver data streams based on a second clock corresponding to the phase shift handoff to generate phase shifted data streams; and latching the phase shifted data streams based on the transmission clock to generate transmission data streams.

17 . The method of claim 16 , further including generating the receiver clock signals and the transmission clock based on a clock generator.

18 . The method of claim 16 , further including determining which of the receiver clock signals is closest to the transmission clock.

19 . The method of claim 16 , further including initializing clock generation circuitry to deterministically handoff the receiver input to the transmission data streams.

20 . The method of claim 16 , further including serializing the transmission data streams to generate transmission data stream.

Assignees

• Texas Instruments Inc

Inventors

• Xavier Ani
• Venkataraman Jagannathan

Classifications

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/018528

  with at least one differential stage · CPC title

• H04L7/0045

  Correction by a latch cascade · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04L7/0012 Primary

  by comparing receiver clock with transmitter clock · CPC title