Top plate sampling circuit including input-dependent dual clock boost circuits

Patent metadata

Field	Value
Publication number	US-10439628-B2
Application number	US-201816104978-A
Country	US
Kind code	B2
Filing date	Aug 20, 2018
Priority date	Dec 28, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

First claim

What is claimed is:

1. A system, comprising:
a analog-to-digital converter (ADC);
a sample and hold circuit (SH circuit) coupled to the ADC wherein the SH circuit comprises a sample stage circuit and a hold stage circuit;
wherein the sample stage circuit comprises:
a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal;
a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal;
a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output, the first input-dependent dual clock boost circuit comprising at least one capacitor configured to provide a first boost voltage to the first gate terminal; and
a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal via a second boost circuit output, the second input-dependent dual clock boost circuit comprising at least one capacitor configured to provide a second boost voltage to the second gate terminal;

wherein the hold stage circuit comprises:
a first amplifier transistor coupled to the first top plate sampling capacitor; and
a second amplifier transistor coupled to the second top plate sampling capacitor.

2. The system of claim 1 , wherein:
the first input terminal is configured to receive a first input that is further configured to generate a first sampling voltage across the first top plate sampling capacitor; and
the second input terminal is configured to receive a second input that is further configured to generate a second sampling voltage across the second top plate sampling capacitor.

3. The system of claim 2 , wherein the first and the second inputs are balanced signals.

4. The system of claim 1 , wherein the first input-dependent dual clock boost circuit further comprising:
a first clock comprising a first boost period and a first charge period; and
a second clock comprising a second boost period and a second charge period, wherein the first and the second boost voltage is provided during the second boost period.

5. The system of claim 4 , wherein the second charge period is delayed relative to the first charge period.

6. The system of claim 2 , wherein the first input-dependent dual clock boost circuit further comprising:
a first clock signal comprising a first boost period and a first charge period, wherein the first clock signal is configured to control a first switch that is coupled to a first voltage node and the first gate terminal; and
a second clock signal comprising a second boost period and a second charge period, wherein the second clock signal is configured to control a second switch and a third switch, wherein the second switch is coupled to a second voltage node and to a first plate of a boost capacitor, a second plate of the boost capacitor is coupled to the third switch, wherein the third switch further couples to ground.

7. The system of claim 6 , wherein a fourth switch configured to be controlled by a clock signal that is inverse to the first clock signal, wherein a fifth switch configured to be controlled by a signal at a first node wherein one end of the fourth switch is coupled at a second node between the second switch and the first plate of a boost capacitor, and another end of the fourth switch is coupled to a third node between the first switch and the first gate terminal.

8. The system of claim 1 , comprising:
a first attenuation cancellation capacitor coupled to the first boost circuit output and the second drain terminal;
a second attenuation cancellation capacitor coupled to the second boost circuit output and the first drain terminal; and
a first common mode capacitor and a second common mode capacitor connected at a common node, wherein a terminal of the first common mode capacitor is coupled to the first drain terminal and a terminal of the second common mode capacitor is coupled to the second drain terminal.

9. The system of claim 1 , wherein the first amplifier transistor comprising a third source terminal, a third drain terminal, and a third gate terminal, wherein the third gate terminal couples to the first top plate sampling capacitor; and
the second amplifier transistor comprising a fourth source terminal, a fourth drain terminal, and a fourth gate terminal, wherein the fourth gate terminal couples to the second top plate sampling capacitor.

10. A system, comprising:
a digital-to-analog converter (DAC);
a sample and hold circuit (SH circuit) coupled to the DAC wherein the SH circuit comprises a sample stage circuit and a hold stage circuit;
wherein the sample stage circuit comprises:
a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal;
a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal;
a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output, the first input-dependent dual clock boost circuit comprising at least one capacitor configured to provide a first boost voltage to the first gate terminal; and
a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal via a second boost circuit output, the second input-dependent dual clock boost circuit comprising at least one capacitor configured to provide a second boost voltage to the second gate terminal;

wherein the hold stage circuit comprises:
a first amplifier transistor coupled to the first top plate sampling capacitor; and
a second amplifier transistor coupled to the second top plate sampling capacitor.

11. The system of claim 10 , wherein:
the first input terminal is configured to receive a first input that is further configured to generate a first sampling voltage across the first top plate sampling capacitor; and
the second input terminal is configured to receive a second input that is further configured to generate a second sampling voltage across the second top plate sampling capacitor.

12. The system of claim 11 , wherein the first and the second inputs are balanced signals.

13. The system of claim 10 , wherein the first input-dependent dual clock boost circuit further comprising:
a first clock comprising a first boost period and a first charge period; and
a second clock comprising a second boost period and a second charge period, wherein the first and the second boost voltage is provided during the second boost period.

14. The system of claim 13 , wherein the second charge period is delayed relative to the first charge period.

15. The system of claim 11 , wherein the first input-dependent dual clock boost circuit further comprising:
a first clock signal comprising a first boost period and a first charge period, wherein the first clock signal is configured to control a first switch that is coupled to a first voltage node and the first gate terminal; and
a second clock signal comprising a second boost period and a second charge period, wherein the second clock si

Assignees

• Texas Instruments Inc

Inventors

• Xavier Ani
• Shrivastava Neeraj
• Mohan Arun

Classifications

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• G06F3/05

  Digital input using the sampling of an analogue quantity at regular intervals of time {, input from a/d converter or output to d/a converter} · CPC title