Signal transmission system for use with eye diagram monitor

Patent metadata

Field	Value
Publication number	US-11855816-B2
Application number	US-202217567775-A
Country	US
Kind code	B2
Filing date	Jan 3, 2022
Priority date	Aug 23, 2021
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.

First claim

The invention claimed is:

1. A signal transmission system comprising:
an equalization filter configured to filter an input signal based at least in part on a feedback signal;
a slicer coupled to the equalization filter and configured to compare the filtered input signal sampled at a plurality of different phases with a threshold and to generate a binary output per unit sample;
a synchronizer coupled to the slicer and configured to compute a phase delay between the input signal at each of the different phases and the binary output for each of the unit samples;
a pattern generator coupled to the synchronizer and configured to generate the feedback signal at a phase adjusted by the phase delay;
a de-serializer coupled to the slicer and configured to parallelize the sampled signal;
a serializer coupled to the equalization filter and configured to serialize the feedback signal; and
a synchronous replica path coupled between the serializer and the de-serializer.

2. The signal transmission system of claim 1 , wherein the equalization filter includes one or more of:
a continuous time linear equalizer (CTLE);
a receiver feed-forward equalizer (Rx FFE) coupled to an output of the CTLE;
a variable gain amplifier (VGA) coupled to an output of the Rx FFE;
a receiver decision-feedback equalizer (Rx DFE) coupled to an output of the slicer; and
a summer coupled to an output of the VGA and an output of the Rx DFE.

3. The signal transmission system of claim 1 , further comprising an eye diagram monitor coupled to the equalization filter and configured to generate an eye diagram based on the filtered signal clocked at the plurality of different phases.

4. A signal transmission system comprising:
an equalization filter configured to filter an input signal based at least in part on a feedback signal;
a slicer coupled to the equalization filter and configured to compare the filtered input signal sampled at a plurality of different phases with a threshold and to generate a binary output per unit sample;
a synchronizer coupled to the slicer and configured to compute a phase delay between the input signal at each of the different phases and the binary output for each of the unit samples;
a pattern generator coupled to the synchronizer and configured to generate the feedback signal at a phase adjusted by the phase delay; and
a delay estimator coupled to the synchronizer and configured to compute a synchronizer delay between the binary output of the slicer and an input of the synchronizer.

5. The signal transmission system of claim 4 , further comprising a dynamic delay control coupled to the pattern generator and configured to advance or delay the pattern generator such that the feedback signal is adjusted by the synchronizer delay.

6. A signal transmission circuit comprising:
an equalization circuit configured to filter an input signal based at least in part on a feedback signal;
a slicer circuit coupled to the equalization circuit, the slicer circuit configured to generate data based on the filtered input signal sampled at a plurality of different phases;
a synchronizer circuit coupled to the slicer circuit and configured to compute a phase delay between the data and the input signal at each of the different phases;
a pattern generator circuit coupled to the synchronizer circuit and configured to generate the feedback signal at a phase adjusted by the phase delay, the input signal and the feedback signal each representing a data test pattern;
a de-serializer circuit coupled to the slicer circuit and configured to parallelize the sampled signal;
a serializer circuit coupled to the equalization circuit and configured to serialize the feedback signal; and
a synchronous replica path between the serializer circuit and the de-serializer circuit.

7. The signal transmission circuit of claim 6 , wherein the equalization circuit includes one or more of:
a continuous time linear equalizer (CTLE) circuit coupled to the input signal;
a receiver feed-forward equalizer (Rx FFE) circuit coupled to an output of the CTLE circuit;
a variable gain amplifier (VGA) circuit coupled to an output of the Rx FFE circuit;
a receiver decision-feedback equalizer (Rx DFE) circuit coupled to an output of the slicer; and
a summer circuit coupled to an output of the VGA circuit and an output of the Rx DFE circuit,
wherein the slicer circuit is coupled to the summer circuit.

8. The signal transmission circuit of claim 6 , further comprising an eye diagram monitor coupled to the equalization circuit and configured to generate an eye diagram based on the filtered signal clocked at the plurality of different phases.

9. A signal transmission circuit comprising:
an equalization circuit configured to filter an input signal based at least in part on a feedback signal;
a slicer circuit having a binary output, the slicer circuit coupled to the equalization circuit, the slicer circuit configured to generate data based on the filtered input signal sampled at a plurality of different phases;
a synchronizer circuit having an input, the equalizer circuit coupled to the slicer circuit and configured to compute a phase delay between the data and the input signal at each of the different phases;
a pattern generator circuit coupled to the synchronizer circuit and configured to generate the feedback signal at a phase adjusted by the phase delay, the input signal and the feedback signal each representing a data test pattern; and
a delay estimator circuit configured to compute a synchronizer delay between the binary output of the slicer circuit and the input of the synchronizer circuit.

10. The signal transmission circuit of claim 9 , further comprising a dynamic delay control circuit configured to advance or delay the pattern generator circuit such that the feedback signal is adjusted by the synchronizer delay.

11. A method for transmitting a signal, the method comprising:
filtering an input signal based at least in part on a feedback signal;
sampling the filtered input signal at a plurality of different phases;
generating data based on the sampled input signal;
computing a first phase delay between the input signal and the data at each of the different phases;
generating the feedback signal at a phase adjusted by the first phase delay;
parallelizing the sampled signal;
serializing the feedback signal; and
computing a second phase delay between the input signal and the sampled signal, wherein the first and second phase delays are different.

12. The method of claim 11 , further comprising generating an eye diagram based on the filtered signal clocked at the plurality of different phases.

13. The method of claim 12 , further comprising synchronizing the data to the feedback signal.

14. The method of claim 11 , wherein the feedback signal is further adjusted by the second phase delay.

Assignees

• Texas Instruments Inc

Inventors

• Manjunath Rakesh
• Ganesan Aravind
• Xavier Ani
• Venkataraman Jagannathan
• Agrawal Abhishek
• Babu Charls
• Kumar Aditya

Classifications

• H04L27/01 Primary

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04L27/20

  Modulator circuits; Transmitter circuits · CPC title

• H04L25/03885 Primary

  adaptive · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/4917

  using multilevel codes · CPC title