Offset correction in high-speed serial link receivers

Patent metadata

Field	Value
Publication number	US-11469928-B2
Application number	US-202117363855-A
Country	US
Kind code	B2
Filing date	Jun 30, 2021
Priority date	Dec 9, 2020
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

First claim

What is claimed is:

1. A receiver circuit, comprising:
an equalizer, comprising:
a plurality of delay stages, each storing one in a sequence of input samples;
a plurality of coefficient gain stages, each associated with and having an input coupled to one of the plurality of delay stages, and each comprising a plurality of differential amplifiers selectable responsive to a selected coefficient value; and
a first summing circuit, having a plurality of inputs, each coupled to an output of one of the plurality of coefficient gain stages;

a slicer, having an input coupled to an output of the first summing circuit; and
offset correction circuitry, comprising:
memory arranged as a plurality of look-up tables (LUTs), each LUT associated with one of the coefficient gain stages, each LUT storing a plurality of offset correction values that are each associated with a coefficient value at the associated coefficient gain stage;
addressing circuitry, for accessing the plurality of LUTs to select offset correction values corresponding to current coefficient values at the associated coefficient gain stages; and
a second summing circuit, for adding the selected offset correction values from the plurality of LUTs, the second summing circuit having an output coupled to an input of the first summing circuit.

2. The receiver circuit of claim 1 , wherein the equalizer is a feed-forward equalizer.

3. The receiver circuit of claim 1 , wherein the offset correction circuitry further comprises:
a descale function, having an input coupled at the output of the second summing circuit, for multiplying a sum of the selected offset correction values from the plurality of LUTs by a descale factor;
and wherein the output of the descale function is coupled to the input of the first summing circuit.

4. The receiver circuit of claim 1 , wherein the slicer comprises:
a plurality of comparators detecting amplitudes at the output of the first summing circuit to quantize each detected amplitude to one of a plurality of levels; and
an error comparator, for determining whether a detected amplitude quantized to either an extreme high level or an extreme low level is greater than or less than that extreme high level or extreme low level;
wherein the offset correction circuitry further comprises:
a first counter, for counting instances of the detected amplitude at the extreme high level being above the extreme high level;
a second counter, for counting instances of the detected amplitude at the extreme high level being below the extreme high level;
a third counter, for counting instances of the detected amplitude at the extreme low level being above the extreme low level;
a fourth counter, for counting instances of the detected amplitude at the extreme low level being below the extreme low level;
counter comparator logic, adapted to:
determine whether both a difference in the contents of the first and second counters and a difference in the contents of the third and fourth counters have reached a trigger value; and
responsive to both differences exceeding the trigger value, providing an adjustment to the equalizer.

5. The receiver circuit of claim 4 , wherein the counter comparator logic is adapted to provide the adjustment to the equalizer by:
responsive to either the contents of the first counter being greater than the contents of the second counter and the contents of the third counter being greater than the contents of the fourth counter, or the contents of the first counter being less than the contents of the second counter and the contents of the third counter being less than the contents of the fourth counter, applying an offset correction to the output of the first summing circuit; and
responsive to either the contents of the first counter being less than the contents of the second counter and the contents of the third counter being greater than the contents of the fourth counter, or the contents of the first counter being greater than the contents of the second counter and the contents of the third counter being less than the contents of the fourth counter, applying a gain correction to the equalizer.

6. The receiver circuit of claim 1 , wherein the equalizer is a feed-forward equalizer;
and further comprising:
a continuous-time equalizer coupled between an input of the receiver and an input of the feed-forward equalizer, and adapted to apply a continuous-time filter to signals received at the input of the receiver.

7. The receiver circuit of claim 1 , wherein the equalizer is a feed-forward equalizer;
and further comprising:
a decision feedback equalizer, having an input coupled to the output of the slicer and an output coupled to an input of the first summing circuit.

8. The receiver circuit of claim 1 , further comprising:
adaptation logic, for determining the selected coefficient values applied to the plurality of coefficient gain stages in the feed-forward equalizer; and
control logic circuitry for storing, in the plurality of LUTs, the offset correction values associated with the selected coefficient values.

9. The receiver circuit of claim 1 , wherein the control logic circuitry is adapted to store the offset correction values by performing a plurality of operations comprising:
zeroing all inputs to the coefficient gain stages;
selecting one of the coefficient gain stages;
applying a zero coefficient value to coefficient gain stages other than the selected coefficient stage;
performing, for each of a plurality of available coefficient values at the selected coefficient gain stage, a plurality of operations comprising:
applying the coefficient value to the selected coefficient gain stage;
detecting an offset at the output of the first summer circuit; and
storing, in the LUT associated with the selected coefficient gain stage at an entry corresponding to the selected coefficient value, an offset correction value corresponding to the detected offset at the output of the first summer circuit; and

repeating the selecting, applying, and performing operations for each of the plurality of coefficient gain stages.

10. The receiver circuit of claim 9 , wherein the offset correction circuitry further comprises:
a descale function, having an input coupled at the output of the second summing circuit, for descaling a sum of the selected offset correction values from the plurality of LUTs by a scaling factor;
wherein the output of the descale function is coupled to the input of the first summing circuit;
and wherein the storing step stores an offset correction value corresponding to the detected offset at the output of the first summer circuit at a higher resolution by the scaling factor than a resolution of the sum of the selected offset correction values.

11. A method of correcting offset in an equalizer including a plurality of delay stages storing a sequence of input samples, a plurality of coefficient gain stages associated with corresponding ones of the plurality of delay stages and comprising a plurality of differential amplifiers selectable responsive to a selected coefficient value, and a summing circuit summing the output of the differential amplifiers, the method comprising the steps of:
at each of a plurality of look-up tables (LUTs) in memory, each LUT associated with one of the coefficient gain stages, retrieving an offset correction value stored in association with the selected coefficient value for that coefficient gain stage;
summing the offset correction values from the plurality of LUTs; and
applying an offset correction to an input of the summing circuit, the offset correction corresponding to the summed offset correction values from the plurality of LUTs

Assignees

• Texas Instruments Inc

Inventors

• Xavier Ani
• Venkataraman Jagannathan
• Aremallapur Nagalinga Swamy Basayya
• Singhal Aviral
• Mohan Arun
• Manjunath Rakesh Chikkanayakanahalli
• Ganesan Aravind
• Adepu Harshavardhan

Classifications

• H04L25/03146 Primary

  with a recursive structure (H04L25/03127 takes precedence) · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L25/061 Primary

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/03859

  shaping using look up tables for partial waveforms · CPC title