Semiconductor product and method for manufacturing a semiconductor product
US-2025125291-A1 · Apr 17, 2025 · US
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Witters Liesbeth patents
Witters Liesbeth is listed as an inventor on 39 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Witters Liesbeth |
| Total patents | 39 |
| First publication | Mar 19, 2015 |
| Latest publication | Apr 17, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Method for Thinning a Semiconductor Substrate
US-2025118564-A1 · Apr 10, 2025 · US
Integration of a III-V construction on a group IV substrate
US-11646200-B2 · May 9, 2023 · US
Method for co-integration of III-V devices with group IV devices
US-11557503-B2 · Jan 17, 2023 · US
Semiconductor fin structure and method of fabricating the same
US-11387350-B2 · Jul 12, 2022 · US
Low parasitic Ccb heterojunction bipolar transistor
US-11355618-B2 · Jun 7, 2022 · US
Integration of a III-V device on a Si substrate
US-11195767-B2 · Dec 7, 2021 · US
Integration of a iii-v construction on a group iv substrate
US-2021358748-A1 · Nov 18, 2021 · US
LOW PARASITIC Ccb HETEROJUNCTION BIPOLAR TRANSISTOR
US-2021167187-A1 · Jun 3, 2021 · US
Method for Co-Integration of III-V Devices with Group IV Devices
US-2021118724-A1 · Apr 22, 2021 · US
Recent patents
Latest publications not already listed above.
Method of forming a semiconductor device comprising at least one germanium nanowire
US-10714595-B2 · Jul 14, 2020 · US
Semiconductor fin structure and method of fabricating the same
US-2020212205-A1 · Jul 2, 2020 · US
Integration of a III-V Device on a Si Substrate
US-2020091003-A1 · Mar 19, 2020 · US
Internal spacers for nanowire semiconductor devices
US-10361268-B2 · Jul 23, 2019 · US
Methods and mask structures for substantially defect-free epitaxial growth
US-10340139-B2 · Jul 2, 2019 · US
Internal spacer formation for nanowire semiconductor devices
US-10269929-B2 · Apr 23, 2019 · US
Germanium Nanowire Fabrication
US-2019013395-A1 · Jan 10, 2019 · US
Method for forming a field effect transistor device having an electrical contact
US-10090393-B2 · Oct 2, 2018 · US
Internal Spacers for Nanowire Semiconductor Devices
US-2018254321-A1 · Sep 6, 2018 · US
Internal Spacer Formation for Nanowire Semiconductor Devices
US-2018166558-A1 · Jun 14, 2018 · US
Method for manufacturing a CMOS device and associated device
US-9972622-B2 · May 15, 2018 · US
Semiconductor devices comprising multiple channels and method of making same
US-9842777-B2 · Dec 12, 2017 · US
Method for Forming a Field Effect Transistor Device Having an Electrical Contact
US-2017141199-A1 · May 18, 2017 · US
Method for forming a transistor structure comprising a fin-shaped channel structure
US-9633891-B2 · Apr 25, 2017 · US
Methods and Mask Structures for Substantially Defect-Free Epitaxial Growth
US-2017040168-A1 · Feb 9, 2017 · US
Semiconductor devices comprising multiple channels and method of making same
US-2017025314-A1 · Jan 26, 2017 · US
Method for providing an NMOS device and a PMOS device on a silicon substrate and silicon substrate comprising an NMOS device and a PMOS device
US-9502415-B2 · Nov 22, 2016 · US
Method for Manufacturing a CMOS Device and Associated Device
US-2016336317-A1 · Nov 17, 2016 · US
Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device
US-9478544-B2 · Oct 25, 2016 · US
Methods using mask structures for substantially defect-free epitaxial growth
US-9476143-B2 · Oct 25, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Imec Vzw | 34 |
| Imec | 5 |
| Samsung Electronics Co Ltd | 1 |
| Micledi Microdisplays Bv | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/024 | 19 |
| H10D84/038 | 16 |
| H10P14/2905 | 11 |
| H01L21/02381 | 11 |
| H10D30/6757 | 10 |