Method for manufacturing a CMOS device and associated device

Patent metadata

Field	Value
Publication number	US-9972622-B2
Application number	US-201615152700-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	May 13, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.

First claim

The invention claimed is:

1. A method for manufacturing a CMOS device, the CMOS comprising a first transistor structure of a first conductivity type in a first region and a second transistor structure of a second conductivity type in a second region, the method comprising:
providing a semiconductor base layer having a main upper surface;
epitaxially growing a germanium layer on the main upper surface of the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed;
performing an anneal step;
thinning the germanium layer;
patterning the germanium layer into fin structures having a longitudinal direction parallel to the main upper surface or into vertical wire structures having a main direction perpendicular on the main upper surface;
laterally embedding the fin structures or vertical wire structures in a dielectric layer;
providing a masking layer covering the first region, leaving the second region exposed;
selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench; and
growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench, wherein at least an upper portion of the protrusion is suitable for being used as a channel structure of the transistor structure of a second conductivity type and wherein at least an upper portion of the germanium fin structure or germanium wire structure is suitable for being used as a channel structure of the transistor structure of a first conductivity type,
wherein the anneal step is performed prior to thinning the germanium layer.

2. The method according to claim 1 , wherein patterning the germanium layer comprises patterning the germanium layer into fin structures, the method thus leading to a fin-type protrusion and a germanium fin structure, further comprising:
selectively removing the masking layer; and
recessing the dielectric layer uniformly such that the upper portion of the protrusion, and the upper portion of the germanium fin structures protrude from the recessed dielectric layer, the upper portion of the protrusion, and the upper portion of the germanium fin structures defining channels of the transistor structure of a first conductivity type and the transistor structure of a second conductivity type.

3. The method according to claim 2 , further comprising thereafter providing source and drain regions to the channels.

4. The method according claim 1 , wherein the semiconductor base layer comprises silicon germanium, and wherein the protrusion comprises a first layer comprising SiGe and a second, upper layer, comprising strained germanium.

5. The method according to claim 1 , wherein the semiconductor base layer comprises a silicon substrate, and wherein the protrusion comprises silicon.

6. The method according to claim 1 , wherein the fin structures or vertical wire structures comprise a width smaller than 10 nm.

7. The method of claim 1 , wherein the anneal step is performed on an unpatterned germanium layer.

8. The method of claim 1 , wherein patterning the germanium layer into fin structures is performed after thinning the germanium layer.

9. The method of claim 1 , wherein the critical thickness comprises a thickness at which lattice defects form in the germanium layer during the epitaxial growth step.

10. A method for manufacturing a CMOS device, the CMOS comprising a first transistor structure of a first conductivity type in a first region and a second transistor structure of a second conductivity type in a second region, the method comprising:
providing a semiconductor base layer having a main upper surface;
epitaxially growing a germanium layer on the main upper surface of the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed;
performing an anneal step;
thinning the germanium layer;
patterning the germanium layer into fin structures having a longitudinal direction parallel to the main upper surface or into vertical wire structures having a main direction perpendicular on the main upper surface;
laterally embedding the fin structures or vertical wire structures in a dielectric layer;
providing a masking layer covering the first region, leaving the second region exposed;
selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench; and
growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench, wherein at least an upper portion of the protrusion is suitable for being used as a channel structure of the transistor structure of a second conductivity type and wherein at least an upper portion of the germanium fin structure or germanium wire structure is suitable for being used as a channel structure of the transistor structure of a first conductivity type,
wherein the anneal step is performed on an unpatterned germanium layer.

11. The method according to claim 1 , wherein patterning the germanium layer comprises patterning the germanium layer into fin structures, the method thus leading to a fin-type protrusion and a germanium fin structure, further comprising:
selectively removing the masking layer; and
recessing the dielectric layer uniformly such that the upper portion of the protrusion, and the upper portion of the germanium fin structures protrude from the recessed dielectric layer, the upper portion of the protrusion, and the upper portion of the germanium fin structures defining channels of the transistor structure of a first conductivity type and the transistor structure of a second conductivity type.

12. The method according to claim 11 , further comprising thereafter providing source and drain regions to the channels.

13. The method according claim 10 , wherein the semiconductor base layer comprises silicon germanium, and wherein the protrusion comprises a first layer comprising SiGe and a second, upper layer, comprising strained germanium.

14. The method according to claim 10 , wherein the semiconductor base layer comprises a silicon substrate, and wherein the protrusion comprises silicon.

15. A method for manufacturing a CMOS device, the CMOS comprising a first transistor structure of a first conductivity type in a first region and a second transistor structure of a second conductivity type in a second region, the method comprising:
providing a semiconductor base layer having a main upper surface;
epitaxially growing a germanium layer on the main upper surface of the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed;
performing an anneal step;
thinning the germanium layer;
patterning the germanium layer into fin structures having a longitudinal direction parallel to the main upper surface or into vertical wire structures having a main direction perpendicular on the main upper surface;
laterally embedding the fin structures or vertical wire structures in a dielectric layer;
providing a masking layer covering the first region, leaving the second region exposed;
selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench; and
growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench, wherein at least an upper portion of the protrusion is sui

Assignees

• Imec Vzw

Inventors

• Witters Liesbeth
• Veloso Anabela

Classifications

• H01L29/0649

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L27/092 Primary

  Electricity · mapped topic