Method for Thinning a Semiconductor Substrate

Patent metadata

Field	Value
Publication number	US-2025118564-A1
Application number	US-202418906945-A
Country	US
Kind code	A1
Filing date	Oct 4, 2024
Priority date	Oct 6, 2023
Publication date	Apr 10, 2025
Grant date	—

Abstract

A layer of semiconductor devices is produced on the frontside of a crystalline semiconductor substrate, in regions separated by dielectric-filled cavities formed previously. Additional layers are then formed on the device layer. The substrate is then flipped and bonded face down to a second substrate, following by the thinning of the crystalline first substrate from the backside. The thinning proceeds as far as possible without removing the full thickness of the first substrate anywhere across its surface. After this, an anisotropic etch is performed to remove additional material of the first substrate. The in-plane dimensions of the device regions separated by the dielectric-filled cavities are specified so that the anisotropic etch is stopped by a crystallographic plane of the substrate material or by the dielectric material in the cavities, before it can reach the devices on the frontside.

First claim

What is claimed is:

1 . A method for producing a thinned semiconductor substrate, comprising:
providing a first substrate having a planar frontside and a planar backside, the first substrate comprising a crystalline semiconductor material on the planar frontside; producing a device layer on the planar frontside of the first substrate, the device layer comprising, in a first area, a plurality of semiconductor devices; producing, in the first area, before producing the device layer, a plurality of cavities from the planar frontside of the first substrate and into the crystalline semiconductor material of the first substrate; at least partially filling the plurality of cavities with a dielectric material; forming an additional dielectric layer over the plurality of semiconductor devices located in the first area; producing an additional layer on top of the device layer, ending with a planar top surface; bonding the first substrate to a second substrate by bonding the planar top surface to a bonding surface of the second substrate; and subsequent to bonding the first substrate to the second substrate, thinning the first substrate from the planar backside such that a uniform layer of the crystalline semiconductor material remains above the plurality of cavities; and subjecting the crystalline semiconductor material to an anisotropic etch process that stops at (i) a specified crystallographic plane of the crystalline semiconductor material, (ii) the dielectric material in at least one of the plurality of cavities, and (iii) the additional dielectric layer, wherein in-plane dimensions of a plurality of regions located between the plurality of cavities and depths of the plurality of cavities are configured such that the anisotropic etch process does not reach the plurality of semiconductor devices.

2 . The method of claim 1 , wherein after the anisotropic etch process, the method further comprises:
depositing a further dielectric material on a thinned backside of the first substrate; and planarizing the further dielectric material and remaining portions of the crystalline semiconductor material to a common planarized surface.

3 . The method of claim 1 , further comprising:
producing a second plurality of cavities in a second area of the first substrate, wherein producing the device layer does not include producing any semiconductor devices in the second area.

4 . The method of claim 3 , wherein a spacing between two adjacent cavities of the second plurality of cavities is configured so that the anisotropic etch process does not reach the planar frontside of the first substrate between the two adjacent cavities of the second plurality of cavities.

5 . The method of claim 1 , wherein the plurality of cavities in the first area define shallow trench isolation (STI) regions.

6 . The method of claim 1 , wherein the crystalline semiconductor material is a crystalline silicon.

7 . The method of claim 6 , wherein the first substrate is a silicon process wafer having the planar frontside and the planar backside oriented along the (100) crystallographic plane of the crystalline silicon.

8 . The method of claim 7 , wherein a plurality of scribe lines divides a plurality of die areas of the silicon process wafer.

9 . The method of claim 8 , wherein at least one cavity of the plurality of cavities is formed in one of the plurality of scribe lines between an adjacent pair of the plurality of die areas.

10 . The method of claim 1 , wherein a plurality of scribe lines divides a plurality of die areas of the first substrate, and at least one cavity of the plurality of cavities is formed in one of the plurality of scribe lines between an adjacent pair of the plurality of die areas.

11 . The method of claim 1 , wherein the in-plane dimensions of the plurality of regions located between the plurality of cavities and the depths of the plurality of cavities are configured such that the anisotropic etch process stops when a V-shaped groove is formed in the crystalline semiconductor material of the first substrate.

12 . The method of claim 1 , wherein the in-plane dimensions of the plurality of regions located between the plurality of cavities and the depths of the plurality of cavities are configured such that the anisotropic etch process stops on crystallographic planes of the crystalline semiconductor material.

13 . The method of claim 1 , wherein the in-plane dimensions of the plurality of regions located between the plurality of cavities and the depths of the plurality of cavities are configured such that the anisotropic etch process stops on the dielectric material in at least one of the plurality of cavities.

14 . The method of claim 1 , wherein the in-plane dimensions of the plurality of regions located between the plurality of cavities and the depths of the plurality of cavities are configured such that the anisotropic etch process stops on the additional dielectric layer.

15 . The method of claim 2 , wherein the further dielectric material is deposited after the plurality of cavities are filled at least partially with the dielectric material, to form a second layer of dielectric material.

16 . The method of claim 15 , wherein the further dielectric material is a pre-metal dielectric (PMD).

17 . The method of claim 16 , wherein the further dielectric material is at least one of SiO 2 or a low-K material.

18 . The method of claim 15 , wherein an interconnect via and a conductor are produced in the second layer of dielectric material.

19 . The method of claim 18 , wherein the interconnect via and the conductor are produced in the second layer of dielectric material by a technique comprising at least one of a single or double damascene process.

20 . The method of claim 1 , wherein the first substrate is bonded to the second substrate at a bonding layer comprising at least one of SiO 2 , SiCN, or a hybrid bonding layer comprising the dielectric material and metal contact pads coplanar therewith.

Assignees

• Imec Vzw

Inventors

• Beyne Eric
• Witters Liesbeth

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title