Integration of a III-V construction on a group IV substrate

Patent metadata

Field	Value
Publication number	US-11646200-B2
Application number	US-202117323540-A
Country	US
Kind code	B2
Filing date	May 18, 2021
Priority date	May 18, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

First claim

What is claimed is:

1. A method for forming a group III-V semiconductor construction over a monocrystalline group IV substrate comprising:
providing an assembly in an epitaxial growth chamber, the assembly comprising the monocrystalline group IV substrate and a first dielectric layer thereon, the first dielectric layer comprising a trench having a bottom that exposes the group IV substrate;
initiating growth of a first III-V structure in the trench to thereby form a bottom part of the first III-V structure inside the trench;
continuing growth out of the trench on top of the bottom part to thereby form a top part of the first III-V structure;
epitaxially growing a sacrificial second III-V structure on the top part of the first III-V structure, the sacrificial second III-V structure being selectively etchable with respect to the first III-V structure in a liquid etching medium;
epitaxially growing a third III-V structure on the sacrificial second III-V structure, the third III-V structure comprising:
a bottom III-V layer on the sacrificial second III-V structure, wherein the sacrificial second III-V structure is selectively etchable with respect to the bottom III-V layer in the liquid etching medium; and
a top III-V layer;

physically disconnecting a first part of the top layer of the third III-V structure from a second part thereof; and
contacting the sacrificial second III-V structure with the liquid etching medium to thereby selectively etch the sacrificial second III-V structure with respect to the first III-V structure and the bottom layer to thereby form a cavity.

2. The method according to claim 1 , wherein the monocrystalline group IV substrate is a monocrystalline silicon substrate.

3. The method according to claim 2 , wherein the group IV substrate exposed at the bottom of the trench is V-shaped.

4. The method according to claim 1 , wherein the group IV substrate exposed at the bottom of the trench is V-shaped.

5. The method according to claim 1 , wherein the first III-V structure comprises In x Ga 1−x As z E 1−z , wherein x is within the range 0 and 1, z is within the range 0 and 1, and E is selected from P, Sb, and N.

6. The method according to claim 1 , wherein the sacrificial second III-V structure comprises InP.

7. The method according to claim 1 , wherein the bottom III-V layer comprises at least one of: In y Al 1−y As, wherein y is from 0.51 to 0.53 or In w Ga 1−w As, wherein w is from 0.52 to 0.54.

8. The method according to claim 7 , wherein the third III-V structure comprises:
a bottom first In y Al 1−y As layer;
an In w Ga 1−w As layer on the bottom first In y Al 1−y As layer;
a second In y Al 1−y As layer over and on the In w Ga 1−w As layer to thereby sandwich the In w Ga 1−w As layer between two In y Al 1−y As layers; and
a top InP layer on the second In y Al 1−y As layer.

9. The method according to claim 7 , wherein the top III-V layer comprises InP.

10. The method according to claim 9 , wherein the third III-V structure comprises:
a bottom first In y Al 1−y As layer;
an In w Ga 1−w As layer on the bottom first In y Al 1−y As layer;
a second In y Al 1−y As layer over and on the In w Ga 1−w As layer to thereby sandwich the In w Ga 1−w As layer between two In y Al 1−y As layers; and
a top InP layer on the second In y Al 1−y As layer.

11. The method according to claim 10 , wherein the III-V semiconductor construction is a field-effect transistor and wherein after physically disconnecting the first part of the top layer of the third III-V structure from the second part thereof, and before contacting the sacrificial second III-V structure with the liquid etching medium the method comprises:
exposing the first part of the top layer of the third III-V structure; and
forming a source, a drain, and a gate stack thereon.

12. The method according to claim 1 , wherein the III-V semiconductor construction is a field-effect transistor and wherein after physically disconnecting the first part of the top layer of the third III-V structure from the second part thereof, and before contacting the sacrificial second III-V structure with the liquid etching medium the method comprises:
exposing the first part of the top layer of the third III-V structure; and
forming a source, a drain, and a gate stack thereon.

13. The method according to claim 12 , wherein the field-effect transistor is a high-electron-mobility transistor.

14. The method according to claim 1 , wherein the III-V semiconductor construction is a field-effect transistor and wherein after contacting the sacrificial second III-V structure with the liquid etching medium, the method comprises:
exposing the first part of the top layer of the third III-V structure; and
forming a source, a drain, and a gate stack thereon.

15. The method according to claim 1 , wherein the top III-V layer comprises InP.

16. The method according to claim 1 , wherein after contacting the sacrificial second III-V structure with the liquid etching medium the method further comprises:
filling the cavity with a dielectric material.

17. The method according to claim 1 , wherein a temperature in the chamber is set to 400° C. or higher when the top part is growing out of the trench.

18. The method according to claim 1 , wherein at least one surfactant is added in the chamber when the top part is growing out of the trench.

Assignees

• Imec Vzw

Inventors

• Witters Liesbeth
• Waldron Niamh
• Walke Amey Mahadev
• Kunert Bernardette
• Mols Yves

Classifications

• H10P14/2912

  Antimonides · CPC title

• H10P14/2909

  Phosphides · CPC title

• H10P14/2908

  Nitrides · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2911 Primary

  Arsenides · CPC title