Method for forming a transistor structure comprising a fin-shaped channel structure

Patent metadata

Field	Value
Publication number	US-9633891-B2
Application number	US-201514924832-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Oct 31, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

First claim

We claim:

1. A method for forming a transistor structure comprising a fin-shaped channel structure, the method comprising:
providing a layer stack in a trench defined by adjacent shallow trench isolation (STI) structures;
recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion;
providing one or more protection layers on the upper portion of the layer stack;
after providing the one or more protection layers, further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack; and
selectively removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other;
wherein providing the layer stack comprises providing an etch stop layer at a position directly below the channel portion, such that the freestanding upper part of the layer stack comprises an etch stop layer at its lower surface after selectively removing the central portion.

2. The method of claim 1 , wherein the channel portion and the STI structures abut a common planar surface, and wherein the method further comprises providing a patterned hard mask layer on top of the layer stack, before recessing the STI structures, the patterned hard mask layer embodying a protection layer for further recessing the STI structures.

3. The method of claim 1 , wherein providing the layer stack comprises providing a second etch stop layer on top of the channel portion, before recessing the STI structures, the second etch stop layer embodying a protection layer for further recessing the STI structures.

4. The method of claim 1 , further comprising growing spacer structures directly adjacent to the exposed upper portion of the layer stack, after recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the spacer structures embodying protection layers for further recessing the STI structures.

5. The method of claim 1 , further comprising, directly after recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, epitaxially growing a wrap-around etch stop layer around the exposed upper portion of the layer stack, the wrap-around etch stop layer embodying a protection layer for further recessing the STI structures.

6. The method of claim 1 , wherein providing the layer stack comprises providing a third etch stop layer in the layer stack, the third etch stop layer being positioned lower in the stack than the first etch stop layer and being separated thereof by a virtual buffer layer, and wherein the third etch stop layer is arranged and adapted for allowing selectively removing the virtual buffer layer in the central portion of the layer stack, such that after the selective removal the upper layer of the lower part of the layer stack is defined by the third etch stop layer.

7. The method of claim 1 , wherein providing the layer stack comprises providing a virtual buffer layer in the central portion of the layer stack, and wherein selectively removing the central portion of the layer stack comprises removing the virtual buffer layer.

8. The method of claim 1 , wherein providing the layer stack comprises providing a virtual buffer layer and a sacrificial layer directly on top of the virtual buffer layer, the sacrificial layer embodying the central portion of the layer stack, and wherein selectively removing the central portion of the layer stack comprises removing the sacrificial layer selectively to the virtual buffer layer.

9. The method of claim 1 , further comprising removing the etch stop layer after removing the central portion of the layer stack.

10. The method of claim 1 , further comprising removing the one or more protection layers, and providing a gate dielectric layer and gate layer stack on the channel layer.

11. The method of claim 1 , further comprising providing a gate dielectric layer and gate layer stack on the freestanding upper part of the stack without removing at least one of the protection layers.

12. The method of claim 5 , further comprising providing a gate dielectric layer and gate layer stack on the freestanding upper part of the stack.

Assignees

• Imec Vzw

Inventors

• Collaert Nadine
• Eneman Geert
• Horiguchi Naoto
• Kim Min-Soo
• Rooyackers Rita
• Veloso Anabela
• Witters Liesbeth

Classifications

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P14/61

  using masks · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/66742

  Electricity · mapped topic