Internal Spacer Formation for Nanowire Semiconductor Devices

Patent metadata

Field	Value
Publication number	US-2018166558-A1
Application number	US-201715822497-A
Country	US
Kind code	A1
Filing date	Nov 27, 2017
Priority date	Dec 9, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

First claim

What is claimed is:

1 . A method comprising:
providing a semiconductor structure comprising at least one fin, wherein the at least one fin comprises a stack of layers of sacrificial material alternated with layers of nanowire material, wherein the semiconductor structure further comprises a dummy gate, wherein the dummy gate partly covers the stack of layers of the at least one fin; removing at least the sacrificial material next to the dummy gate; oxidizing the sacrificial material and the nanowire material next to the dummy gate, resulting respectively in a spacer oxide and in a nanowire oxide; and removing the nanowire oxide until the nanowire oxide is completely removed and at least a part of the spacer oxide is remaining.

2 . The method of claim 1 , wherein the remaining spacer oxide comprises an internal spacer, wherein the internal spacer is a space between nanowires in the semiconductor structure.

3 . The method of claim 1 , further comprising:
removing the nanowire material next to the dummy gate so as to form a trench; and subsequently oxidizing the sacrificial material and the nanowire material.

4 . The method of claim 1 , further comprising:
creating a source-drain by epitaxial growth.

5 . The method of claim 1 , wherein providing a semiconductor structure comprises providing a semiconductor structure wherein the nanowire material is Ge and the sacrificial layer material is SiGe.

6 . The method of claim 5 , wherein providing a semiconductor structure comprises providing a semiconductor structure wherein a Ge content in SiGe is lower than 80%.

7 . The method of claim 5 , wherein removing the nanowire oxide is performed using a water-based non-oxidizing solution as an etchant.

8 . The method of claim 5 , wherein oxidizing the sacrificial material and the nanowire material is performed according to tuning parameters, and wherein the method further comprises:
while oxidizing the sacrificial material and the nanowire material, adjusting the tuning parameters so as to control a Ge content in the spacer oxide.

9 . The method of claim 5 , further comprising:
subsequent to oxidizing the sacrificial material and the nanowire material, annealing the semiconductor structure so as to control a Ge content in an oxidized SiGe layer.

10 . The method of claim 5 , wherein oxidizing the SiGe is performed without water or HCl soluble.

11 . The method of claim 5 , wherein the nanowire oxide comprises Ge-oxide, wherein removing the Ge-oxide is performed with HCl.

12 . The method of claim 1 , wherein providing a semiconductor structure comprises providing a semiconductor structure wherein the nanowire material comprises Si and the sacrificial layer material comprises SiGe.

13 . The method of claim 12 , wherein removing the nanowire oxide is performed using HF as an etchant.

14 . The method of claim 12 , wherein removing the sacrificial material next to the dummy gate is performed with a water-based selective etch without the presence of HF.

Assignees

• Imec Vzw

Inventors

• Wostyn Kurt
• Witters Liesbeth
• Mertens Hans

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/66553 Primary

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic