Multiply-Instantiated Block Modeling For Circuit Component Placement In Integrated Circuit
US-2024143885-A1 · May 2, 2024 · US
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Sinha Debjit patents
Sinha Debjit is listed as an inventor on 43 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sinha Debjit |
| Total patents | 43 |
| First publication | Jan 6, 2015 |
| Latest publication | May 2, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Statistical timing analysis considering multiple-input switching
US-11093675-B1 · Aug 17, 2021 · US
Efficient projection based adjustment evaluation in static timing analysis of integrated circuits
US-11017137-B2 · May 25, 2021 · US
Efficient projection based adjustment evaluation in static timing analysis of integrated circuits
US-2021103637-A1 · Apr 8, 2021 · US
Apportionment aware hierarchical timing optimization
US-10970455-B1 · Apr 6, 2021 · US
Parallel access to running electronic design automation (EDA) application
US-10929567-B2 · Feb 23, 2021 · US
Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs
US-10831954-B1 · Nov 10, 2020 · US
Variable accuracy incremental timing analysis
US-10747925-B1 · Aug 18, 2020 · US
Variable accuracy incremental timing analysis
US-2020242205-A1 · Jul 30, 2020 · US
Parallel access to running eda application
US-2019286830-A1 · Sep 19, 2019 · US
Recent patents
Latest publications not already listed above.
Parallel access to running electronic design automation (EDA) application
US-10387682-B2 · Aug 20, 2019 · US
Multi-sided variations for creating integrated circuits
US-10380286-B2 · Aug 13, 2019 · US
Multi-sided variations for creating integrated circuits
US-10380289-B2 · Aug 13, 2019 · US
Multi-sided variations for creating integrated circuits
US-10346569-B2 · Jul 9, 2019 · US
Incremental common path pessimism analysis
US-10325059-B2 · Jun 18, 2019 · US
Accurate statistical timing for boundary gates of hierarchical timing models
US-10169527-B2 · Jan 1, 2019 · US
Parallel access to running eda application
US-2018357433-A1 · Dec 13, 2018 · US
Parallel access to running eda application
US-2018357436-A1 · Dec 13, 2018 · US
Multi-sided variations for creating integrated circuits
US-2018239860-A1 · Aug 23, 2018 · US
Multi-sided variations for creating integrated circuits
US-2018239859-A1 · Aug 23, 2018 · US
Multi-sided variations for creating integrated circuits
US-2018239858-A1 · Aug 23, 2018 · US
Accurate statistical timing for boundary gates of hierarchical timing models
US-9940431-B2 · Apr 10, 2018 · US
Accurate statistical timing for boundary gates of hierarchical timing models
US-2018075183-A1 · Mar 15, 2018 · US
Distributed timing analysis of a partitioned integrated circuit design
US-9916405-B2 · Mar 13, 2018 · US
Incremental common path pessimism analysis
US-2018046748-A1 · Feb 15, 2018 · US
Incremental common path pessimism analysis
US-9836572-B2 · Dec 5, 2017 · US
Statistical timing using macro-model considering statistical timing value entry
US-9798843-B2 · Oct 24, 2017 · US
Distributed timing analysis of a partitioned integrated circuit design
US-2017242945-A1 · Aug 24, 2017 · US
Variation-aware timing analysis using waveform construction
US-9710594-B2 · Jul 18, 2017 · US
Accurate statistical timing for boundary gates of hierarchical timing models
US-2017199956-A1 · Jul 13, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 43 |
| Google Llc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F30/3312 | 32 |
| G06F2119/12 | 30 |
| G06F30/398 | 20 |
| G06F17/5081 | 20 |
| G06F17/5031 | 19 |