Incremental common path pessimism analysis

Patent metadata

Field	Value
Publication number	US-9836572-B2
Application number	US-201514946043-A
Country	US
Kind code	B2
Filing date	Nov 19, 2015
Priority date	Nov 19, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.

First claim

What is claimed is:

1. A computer-implemented method of performing incremental common path pessimism analysis in integrated circuit design, the method comprising:
performing, using a processor, common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism;
identifying one or more post-CPPR critical paths following the CPPR analysis that provides the timing credit to the one or more paths that are subject to common path pessimism;
setting flags for critical nodes of the one or more post-CPPR critical paths;
performing a design fix to address the one or more post-CPPR critical paths;
applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths, wherein the identifying the seed points is by identifying the critical nodes that meet one or more of the following criteria: the critical node is a sink of an edge added as a result of the performing the design fix, the critical node is a source or sink of an edge deleted as a result of the performing the design fix, the critical node is a sink of an edge with a changed arrival time based on the performing the design fix, and the critical node is a source of an edge with a changed required arrival time based on the performing the design fix; and
invalidating and re-performing the CPPR analysis only for paths in a fan-out cone from the seed points, wherein the integrated circuit design resulting from the incremental common path pessimism analysis is implemented as a physical implementation of an integrated circuit.

2. The computer-implemented method according to claim 1 , wherein the identifying the one or more post-CPPR critical paths is based on post-CPPR path slack of the one or more post-CPPR critical paths.

3. The computer-implemented method according to claim 1 , wherein the identifying the one or more post-CPPR critical paths is based on a threshold post-CPPR path slack.

4. The computer-implemented method according to claim 1 , wherein the setting the flags includes flagging every critical node in each of the one or more post-CPPR critical paths.

5. The computer-implemented method according to claim 1 , wherein the setting the flags includes setting two flags for every critical node in each of the one or more post-CPPR critical paths, the two flags associated with an early mode and a late mode.

6. The computer-implemented method according to claim 1 , wherein the setting the flags includes setting one flag associated with each endpoint for every critical node in each of the one or more post-CPPR critical paths.

7. The computer-implemented method according to claim 1 , wherein the invalidating and re-performing the CPPR analysis is performed only for paths in a fan-out cone of the seed points.

8. A system to perform incremental common path pessimism analysis in integrated circuit design, the system comprising:
a memory device configured to store a set of rules; and
a processor configured to perform common path pessimism removal (CPPR) analysis to adjust delay in one or more paths that are subject to common path pessimism, identify one or more post-CPPR critical paths following the CPPR analysis that provides timing credit to the one or more paths that are subject to common path pessimism, set flags for critical nodes of the one or more post-CPPR critical paths, perform a design fix to address the one or more post-CPPR critical paths, apply the set of rules based on the design fix and the flags to identify seed points among the critical nodes, and invalidate and re-perform the CPPR analysis only for paths in a fan-out cone from the seed points, wherein the processor identifies the seed points by identifying the critical nodes that meet one or more of the following criteria according to the set of rules: the critical node is a sink of an edge added as a result of the performing the design fix, the critical node is a source or sink of an edge deleted as a result of the performing the design fix, the critical node is a sink of an edge with a changed arrival time based on the performing the design fix, and the critical node is a source of an edge with a changed required arrival time based on the performing the design fix, wherein the integrated circuit design is implemented as a physical implementation of an integrated circuit.

9. The system according to claim 8 , wherein the processor identifies the one or more post-CPPR critical paths based on post-CPPR path slack of the one or more post-CPPR critical paths.

10. The system according to claim 8 , wherein the processor identifies the one or more post-CPPR critical paths based on a threshold post-CPPR path slack.

11. The system according to claim 8 , wherein the processor sets the flags by flagging every critical node in each of the one or more post-CPPR critical paths.

12. The system according to claim 8 , wherein the processor sets the flags by setting two flags for every critical node in each of the one or more post-CPPR critical paths, the two flags associated with an early mode and a late mode, or by setting one flag associated with each endpoint for every critical node in each of the one or more post-CPPR critical paths.

13. A computer program product for performing incremental common path pessimism analysis in integrated circuit design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
performing common path pessimism removal (CPPR) analysis to adjust delay in one or more paths that are subject to common path pessimism;
identifying one or more post-CPPR critical paths following the CPPR analysis that provides timing credit to the one or more paths that are subject to common path pessimism;
setting flags for critical nodes of the one or more post-CPPR critical paths;
performing a design fix to address the one or more post-CPPR critical paths;
applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths, wherein the identifying the seed points is by identifying the critical nodes that meet one or more of the following criteria: the critical node is a sink of an edge added as a result of the performing the design fix, the critical node is a source or sink of an edge deleted as a result of the performing the design fix, the critical node is a sink of an edge with a changed arrival time based on the performing the design fix, and the critical node is a source of an edge with a changed required arrival time based on the performing the design fix; and
invalidating and re-performing the CPPR analysis only for paths in a fan-out cone from the seed points, wherein the integrated circuit design resulting from the incremental common path pessimism analysis is implemented as a physical implementation of an integrated circuit.

14. The computer program product according to claim 13 , wherein the identifying the one or more post-CPPR critical paths is based on post-CPPR path slack of the one or more post-CPPR critical paths.

15. The computer-implemented method according to claim 13 , wherein the identifying the one or more post-CPPR critical paths is based on a threshold post-CPPR path slack.

16. The computer program product according to claim 13 , wherein the setting the flags includes flagging every critical node in each of the one or more post-CPPR critical paths, setting two flags for every critical node

Assignees

• IBM

Inventors

• Huang Tsung-Wei
• Kalafala Kerim
• Rao Vasant B
• Sinha Debjit
• Venkateswaran Natesan

Classifications

• G06F30/30

  Circuit design · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F17/5045

  Physics · mapped topic