Accurate statistical timing for boundary gates of hierarchical timing models

Patent metadata

Field	Value
Publication number	US-9940431-B2
Application number	US-201614990212-A
Country	US
Kind code	B2
Filing date	Jan 7, 2016
Priority date	Jan 7, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.

First claim

What is claimed is:

1. A method of improving performance of a semiconductor chip design, the method comprising:
determining, by a computer processor, a hierarchical arrangement of the semiconductor chip design, the hierarchical arrangement including a plurality of arcs located at different levels internal to the semiconductor chip design, wherein the different levels include a macro level, a unit level and a core level;
determining, by the computer processor, first timing characteristics of at least one first arc in the macro level based on a load applied to the at least one first arc;
generating a macro timing model of the macro level based on the first timing characteristics;
determining, by the computer processor, second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics and the macro timing level, wherein a portion of the second timing characteristics is determined irrespective of the load; and
determining the second timing characteristics further based on at least one of a load applied to the at least one first arc and an input voltage applied to the at least one first arc,
wherein the load includes a first capacitance load applied to the output of at least one first arc and a second capacitance load applied to an output of the at least one second arc, and wherein the input voltage changes from a first voltage level to a second voltage level to define an input slew rate, and
wherein an input slew rate is implemented in the semiconductor design and the semiconductor chip design is provided for semiconductor chip fabrication.

2. The method of claim 1 , further comprising determining the second timing characteristics according to an internal gate characterization scheme in response to characterizing a respective arc based on a varying slew rate irrespective of the load.

3. The method of claim 1 , further comprising determining the second timing characteristics according to a boundary gate characterization scheme in response to characterizing a respective arc based on a varying slew rate with respect to the load.

4. The method of claim 1 , further comprising determining original rules of load-dependent gate segments, and determining the second timing characteristics according to a boundary gate characterization scheme that is based on process manufacturing, voltage, temperature (PVT) tables generated according to the original rules.

5. The method of claim 1 , further comprising determining at least one boundary gate included in a macro cell included in the macro level, and determining the second timing characteristics according to a boundary gate characterization scheme in response to maintaining at least one pointer that points to at least one of the macro cell, and original timing rules of the macro cell.

6. A system to improve performance of a semiconductor chip design, the system comprising:
a hierarchical analysis module including a hardware controller configured to determine a hierarchical arrangement of the semiconductor chip design, the hierarchical arrangement including a plurality of arcs located at different levels internal to the semiconductor chip design, wherein the different levels include a macro level, a unit level and a core level;
a macro model module configured to generate a macro timing model of the macro level based on the first timing characteristics; and
a timing/load analysis module including a hardware controller configured to determine first timing characteristics of at least one first arc in the macro level based on a load applied to the at least one first arc, and to determine second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, wherein a portion of the second timing characteristics is determined irrespective of the load,
wherein an input slew rate is implemented in the semiconductor design and the semiconductor chip design is provided for semiconductor chip fabrication,
wherein the timing/load analysis module includes a hardware controller configured to determine second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the macro timing model,
wherein determining the second timing characteristics is based on at least one of a load applied to the at least one first arc and an input voltage applied to the at least one first arc, and
wherein the load includes a first capacitance load applied to an output of the at least one first arc and a second capacitance load applied to an output of the at least one second arc, and wherein the input voltage changes from a first voltage level to a second voltage level to define an input slew rate.

7. The system of claim 6 , wherein the second timing characteristics are determined in response to performing both an internal gate characterization scheme and a boundary gate characterization scheme, the internal gate characterization scheme characterizing a respective arc based on a varying slew rate irrespective of the load, and the boundary gate characterization scheme characterizing a respective arc based on a varying slew rate with respect to the load.

8. The system of claim 6 , wherein the second timing characteristics are based on original rules of load-dependent gate segments, and wherein the second timing characteristics are determined according to a boundary gate characterization scheme that is based on process manufacturing, voltage, temperature (PVT) tables generated according to the original rules.

9. The system of claim 6 , wherein the second timing characteristics are determined in response to maintaining at least one pointer that points to at least one of a macro cell included in the macro level and original timing rules of the macro cell.

10. The system of claim 6 , wherein the macro model module generates a look-up table (LUT) including at least one timing entry that indexes the input slew rate with respect to the load of a respective arc.

11. The system of claim 10 , wherein each timing entry indicates a time duration at which a switching signal is generated at the output of the respective arc in response to applying the input voltage.

12. A computer program product to improve performance of a semiconductor chip design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an electronic computer processor to perform operations comprising:
determining, by a computer processor, a hierarchical arrangement of the semiconductor chip design, the hierarchical arrangement including a plurality of arcs located at different levels internal to the semiconductor chip design, wherein the different levels include a macro level, a unit level and a core level;
determining, by the computer processor, first timing characteristics of at least one first arc in the macro level based on a load applied to the at least one first arc;
generating a macro timing model of the macro level based on the first timing characteristics;
determining, by the computer processor, second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics and the macro timing level, wherein a portion of the second timing characteristics is determined irrespective of the load;
determining the second timing characteristics further based on at least one of a load applied to the at least one first arc and an input voltage applied to the at least one first arc,
wherein the load includes a first capacitance

Assignees

• IBM

Inventors

• Gupta Hemlata
• Sinha Debjit
• Visweswariah Chandramouli

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5031

  Physics · mapped topic