Distributed timing analysis of a partitioned integrated circuit design

Patent metadata

Field	Value
Publication number	US-9916405-B2
Application number	US-201615049501-A
Country	US
Kind code	B2
Filing date	Feb 22, 2016
Priority date	Feb 22, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A method, system, and computer program product perform distributed timing analysis of an integrated circuit design. Aspects include dividing the integrated circuit design into non-overlapping design partitions, each design partition including nodes and edges, each edge interconnecting a pair of the nodes. Aspects also include identifying speculative nodes among the nodes, each speculative node having at least one and less than all timing inputs available and being associated with a speculative processing task, and identifying non-speculative nodes among the nodes, each non-speculative node having all timing inputs available and being associated with a non-speculative processing task. Assigning each of the non-speculative processing tasks to a respective processor of a processing system specific to each design partition for timing analysis processing is done prior to assigning any of the speculative processing tasks.

First claim

What is claimed is:

1. A computer-implemented method of performing distributed timing analysis of an integrated circuit design, the method comprising:
dividing the integrated circuit design into non-overlapping design partitions, each design partition including nodes and edges, each edge interconnecting a pair of the nodes;
identifying, for each design partition, speculative nodes among the nodes, each speculative node having at least one and less than all timing inputs available and being associated with a speculative processing task;
identifying, for each design partition, non-speculative nodes among the nodes, each non-speculative node having all timing inputs available and being associated with a non-speculative processing task;
assigning each of the non-speculative processing task to a respective processor of a processing system specific to each design partition for timing analysis processing prior to assigning any of the speculative processing tasks; and
obtaining a physical implementation of an integrated circuit according to the integrated circuit design that results from the distributed timing analysis.

2. The computer-implemented method according to claim 1 , further comprising ranking the speculative nodes.

3. The computer-implemented method according to claim 2 , wherein the ranking the speculative nodes is based on a confidence score for each of the speculative nodes.

4. The computer-implemented method according to claim 2 , wherein the ranking each of the speculative nodes is based on a cost associated with each of the speculative nodes given by a number of the one or more timing inputs not available for the speculative node.

5. The computer-implemented method according to claim 2 , wherein the assigning each of the speculative processing tasks to the respective processor of the processing system is in an order based on the ranking of the associated speculative nodes.

6. The computer-implemented method according to claim 1 , further comprising including a tag with an output of the timing analysis to indicate whether the timing analysis is associated with one of the speculative processing tasks or one of the non-speculative processing tasks.

7. The computer-implemented method according to claim 6 , further comprising verifying the output of the timing analysis based on the tag indicating that the timing analysis is associated with one of the speculative processing tasks.

8. A system to perform timing analysis of a design partition of an integrated circuit design, the system comprising:
a memory device configured to store the design partition of the integrated circuit design, a plurality of the design partitions representing non-overlapping portions of the integrated circuit design and the design partition including nodes and edges, each edge interconnecting a pair of nodes; and
one or more processors configured to identify speculative nodes among the nodes, each speculative node having at least one and less than all timing inputs available and being associated with a speculative processing task, identify non-speculative nodes among the nodes, each non-speculative node having all timing inputs available and being associated with a non-speculative processing task, and perform timing analysis of the non-speculative processing tasks prior to performing timing analysis of any of the speculative processing tasks, wherein each of the one or more processors processes one of the speculative processing tasks or one of the non-speculative processing tasks at a time, wherein a physical implementation of an integrated circuit is obtained according to the integrated circuit design that results from the timing analysis.

9. The system according to claim 8 , where the one or more processors ranks the speculative nodes.

10. The system according to claim 9 , wherein the one or more processors ranks the speculative nodes based on a confidence score for each of the speculative nodes.

11. The system according to claim 9 , wherein the one or more processors rank the speculative nodes based on a cost associated with each of the speculative nodes given by a number of the one or more timing inputs not available for the speculative node.

12. The system according to claim 9 , wherein the one or more processors perform timing analysis of speculative processing tasks in an order based on the rank of the associated speculative node.

13. The system according to claim 8 , wherein the one or more processors include a tag with an output of the timing analysis to indicate whether the timing analysis is associated with one of the speculative processing tasks or one of the non-speculative processing tasks.

14. The system according to claim 13 , wherein the one or more processors verify the output of the timing analysis based on the tag indicating that the timing analysis is associated with one of the speculative processing tasks.

15. A computer program product for performing timing analysis of a design partition of an integrated circuit design, the design partition representing a portion of the integrated circuit design and including nodes and edges, each edge interconnecting a pair of the nodes, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to perform a method comprising:
identifying speculative nodes among the nodes, each speculative node having at least one and less than all timing inputs available and being associated with a speculative processing task;
identifying non-speculative nodes among the nodes, each non-speculative node having all timing inputs available and being associated with a non-speculative processing task; and
assigning each of the non-speculative processing tasks to a respective processor among the one or more processors for timing analysis processing prior to assigning any of the speculative processing tasks, wherein physical implementation of an integrated circuit is obtained according to the integrated circuit design that results from the timing analysis.

16. The computer program product according to claim 15 , further comprising ranking the speculative nodes, wherein the assigning each of the speculative processing tasks to the respective processor of the processing system is in an order based on the ranking of the associated speculative nodes.

17. The computer program product according to claim 16 , wherein the ranking the speculative nodes is based on a confidence score for each of the speculative nodes.

18. The computer program product according to claim 16 , wherein the ranking each of the speculative nodes is based on a cost associated with each of the speculative nodes given by a number of the one or more timing inputs not available for the speculative node.

19. The computer program product according to claim 15 , further comprising including a tag with an output of the timing analysis to indicate whether the timing analysis is associated with one of the speculative processing tasks or one of the non-speculative processing tasks.

20. The computer program product according to claim 19 , further comprising verifying the output of the timing analysis based on the tag indicating that the timing analysis is associated with one of the speculative processing tasks.

Assignees

• IBM

Inventors

• Huang Tsung-Wei
• Kalafala Kerim
• Sinha Debjit
• Venkateswaran Natesan

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F2111/02

  CAD in a network environment, e.g. collaborative CAD or distributed simulation · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title