Bottom contact for stacked GAA FET

Patent metadata

Field	Value
Publication number	US-12324236-B2
Application number	US-202117522015-A
Country	US
Kind code	B2
Filing date	Nov 9, 2021
Priority date	Nov 9, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.

First claim

The invention claimed is:

1. A method for constructing a semiconductor device, the method comprising:
forming a plurality of fins over a nanosheet stack and a substrate;
forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape;
forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer;
forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region;
forming n-type epitaxial regions between the plurality of fins;
forming p-type epitaxy regions over the n-type epitaxial regions; and
forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region of the n-type epitaxial regions.

2. The method of claim 1 , wherein each of the plurality of fins formed over the nanosheet stack has a different shape.

3. The method of claim 1 , wherein an epitaxial spacer separates the n-type epitaxial regions from the p-type epitaxy regions.

4. The method of claim 1 , further comprising replacing the plurality of fins with work function metal (WFM) after formation of the p-type epitaxy regions.

5. The method of claim 1 , wherein a first spacer of the spacers formed between the nanosheet stack and one or more of the plurality of fins defines a substantially stepped configuration.

6. The method of claim 1 , wherein a second spacer of the spacers formed between the nanosheet stack and one or more of the plurality of fins is substantially flat.

7. The method of claim 1 , wherein a third spacer of the spacers formed between the nanosheet stack and one or more of the plurality of fins defines a substantially inverted L-shaped configuration.

8. The method of claim 1 , wherein a second contact is formed to a top surface of a p-type epitaxial region of the p-type epitaxial regions.

9. The method of claim 1 , wherein a third contact is formed through a p-type epitaxial region of the p-type epitaxial regions to a top surface of a respective n-type epitaxial region of the n-type epitaxial regions.

10. A method for constructing a stacked gate-all-around field effect transistor (GAA FET), the method comprising:
forming a plurality of fins over a nanosheet stack and a substrate;
forming barrier spacers over shallow trench isolation (STI) regions;
forming n-type epitaxial regions between the plurality of fins;
forming p-type epitaxy regions over the n-type epitaxial regions; and
forming a first contact extending vertically through the GAA FET and extending laterally away from the barrier spacers to directly contact a sidewall of an n-type epitaxial region of the n-type epitaxial regions.

11. The method of claim 10 , further comprising forming spacers between the nanosheet stack and one or more of the plurality of fins.

12. The method of claim 11 , wherein each spacer defines a different shape.

13. The method of claim 11 , wherein a first spacer of the spacers formed between the nanosheet stack and one or more of the plurality of fins defines a substantially stepped configuration.

14. The method of claim 11 , wherein a second spacer of the spacers formed between the nanosheet stack and one or more of the plurality of fins is substantially flat.

15. The method of claim 11 , wherein a third spacer of the spacers formed between the nanosheet stack and one or more of the plurality of fins defines a substantially inverted L-shaped configuration.

16. The method of claim 10 , wherein an epitaxial spacer separates the n-type epitaxial regions from the p-type epitaxy regions.

17. The method of claim 10 , further comprising replacing the plurality of fins with work function metal (WFM) after formation of the p-type epitaxy regions.

18. The method of claim 10 ,
wherein a second contact is formed to a top surface of a first p-type epitaxial region of the p-type epitaxial regions; and
wherein a third contact is formed through a second p-type epitaxial region of the p-type epitaxial regions to a top surface of a respective n-type epitaxial region of the n-type epitaxial regions.

19. A stacked gate-all-around field effect transistor (GAA FET) comprising:
barrier spacers disposed over shallow trench isolation (STI) regions;
n-type epitaxial regions formed between the plurality of fins;
p-type epitaxy regions formed over the n-type epitaxial regions; and
a first contact extending vertically through the GAA FET and extending laterally away from the barrier spacers to directly contact a sidewall of an n-type epitaxial region of the n-type epitaxial regions.

20. The stacked GAA FET of claim 19 , wherein spacers are disposed between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape.

Assignees

• IBM

Inventors

• Seshadri Indira
• Sieg Stuart
• Fan Su Chen

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title