Using a same mask for direct print and self-aligned double patterning of nanosheets

Patent metadata

Field	Value
Publication number	US-12080559-B2
Application number	US-202117546443-A
Country	US
Kind code	B2
Filing date	Dec 9, 2021
Priority date	Jul 17, 2019
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate;
a nanosheet stack disposed over the substrate, the nanosheet stack comprising alternating layers of a sacrificial material and a channel material, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors;
a hard mask stack disposed over the nanosheet stack;
a patterning layer disposed over the hard mask stack; and
a lithographic mask disposed over the patterning layer, the lithographic mask defining (i) one or more first regions having a first width for direct printing of one or more fins of the first width in the nanosheet stack and the substrate and (ii) one or more second regions having a second width for setting the spacing between two or more fins of the second width in the nanosheet stack and the substrate using self-aligned double patterning;
wherein the second width is less than the first width.

2. The semiconductor structure of claim 1 , wherein the lithographic mask covers the one or more first regions and the one or more second regions.

3. The semiconductor structure of claim 1 , wherein the lithographic mask exposes the one or more first regions and the one or more second regions.

4. The semiconductor structure of claim 1 , wherein the nanosheet stacks over the one or more fins of the first width provide channels for n-type nanosheet field-effect transistors and the nanosheet stacks disposed over the one or more fins of the second width provide channels for p-type nanosheet field-effect transistors.

5. The semiconductor structure of claim 1 , wherein the patterning layer comprises amorphous silicon.

6. The semiconductor structure of claim 1 , wherein the patterning layer comprises amorphous carbon.

7. The semiconductor structure of claim 1 , wherein the lithographic mask comprises a photoresist material.

8. The semiconductor structure of claim 1 , wherein the hard mask stack comprises a padding oxide layer and a nitride-oxide-nitride hard mask stack disposed over the padding oxide layer.

9. A semiconductor structure comprising:
a substrate;
a nanosheet stack disposed over the substrate, the nanosheet stack comprising alternating layers of a sacrificial material and a channel material, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors;
a hard mask stack disposed over the nanosheet stack;
a patterning layer disposed over the hard mask stack; and
a lithographic mask disposed over the patterning layer, the lithographic mask covering (i) one or more first regions having a first width for direct printing of one or more fins of the first width in the nanosheet stack and the substrate and (ii) one or more second regions having a second width for setting the spacing between two or more fins of the second width in the nanosheet stack and the substrate using self-aligned double patterning;
wherein the second width is less than the first width.

10. The semiconductor structure of claim 9 , wherein the nanosheet stacks over the one or more fins of the first width provide channels for n-type nanosheet field-effect transistors and the nanosheet stacks disposed over the one or more fins of the second width provide channels for p-type nanosheet field-effect transistors.

11. The semiconductor structure of claim 9 , wherein the patterning layer comprises amorphous silicon.

12. The semiconductor structure of claim 9 , wherein the patterning layer comprises amorphous carbon.

13. The semiconductor structure of claim 9 , wherein the lithographic mask comprises a photoresist material.

14. The semiconductor structure of claim 9 , wherein the hard mask stack comprises a padding oxide layer and a nitride-oxide-nitride hard mask stack disposed over the padding oxide layer.

15. A semiconductor structure comprising:
a substrate;
a nanosheet stack disposed over the substrate, the nanosheet stack comprising alternating layers of a sacrificial material and a channel material, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors;
a hard mask stack disposed over the nanosheet stack;
a patterning layer disposed over the hard mask stack; and
a lithographic mask disposed over the patterning layer, the lithographic mask exposing (i) one or more first regions having a first width for direct printing of one or more fins of the first width in the nanosheet stack and the substrate and (ii) one or more second regions having a second width for setting the spacing between two or more fins of the second width in the nanosheet stack and the substrate using self-aligned double patterning;
wherein the second width is less than the first width.

16. The semiconductor structure of claim 15 , wherein the nanosheet stacks over the one or more fins of the first width provide channels for n-type nanosheet field-effect transistors and the nanosheet stacks disposed over the one or more fins of the second width provide channels for p-type nanosheet field-effect transistors.

17. The semiconductor structure of claim 15 , wherein the patterning layer comprises amorphous silicon.

18. The semiconductor structure of claim 15 , wherein the patterning layer comprises amorphous carbon.

19. The semiconductor structure of claim 15 , wherein the lithographic mask comprises a photoresist material.

20. The semiconductor structure of claim 15 , wherein the hard mask stack comprises a padding oxide layer and a nitride-oxide-nitride hard mask stack disposed over the padding oxide layer.

Assignees

• IBM

Inventors

• Sieg Stuart
• Dechene Daniel James
• Miller Eric

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title