Using a same mask for direct print and self-aligned double patterning of nanosheets

Patent metadata

Field	Value
Publication number	US-11257681-B2
Application number	US-201916514235-A
Country	US
Kind code	B2
Filing date	Jul 17, 2019
Priority date	Jul 17, 2019
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors;
forming a hard mask stack over the nanosheet stack;
forming a patterning layer over the hard mask stack; and
patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning;
wherein the second width is less than the first width.

2. The method of claim 1 , wherein the lithographic mask is patterned over the patterning layer such that the lithographic material covers the one or more first regions and the one or more second regions.

3. The method of claim 1 , wherein the lithographic mask is patterned over the patterning layer such that lithographic material exposes the one or more first regions and the one or more second regions.

4. The method of claim 1 , wherein the hard mask stack comprises a padding oxide layer and a nitride-oxide-nitride hard mask stack over the padding oxide layer.

5. The method of claim 1 , wherein the patterning layer comprises amorphous silicon (a-Si).

6. A method of forming a semiconductor structure comprising:
forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors;
forming a hard mask stack over the nanosheet stack;
forming a patterning layer over the hard mask stack; and
patterning a lithographic mask over the patterning layer, the lithographic mask covering (i) one or more first regions of a top surface of the patterning layer for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions of the top surface of the patterning layer for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning;
wherein the second width is less than the first width.

7. The method of claim 6 , further comprising:
etching portions of the patterning layer exposed by the lithographic mask to form a plurality of patterning mandrels; and
removing the lithographic mask.

8. The method of claim 7 , further comprising:
depositing a spacer material over the plurality of patterning mandrels and portions of a top surface of the hard mask stack exposed by etching of the portions of the patterning layer exposed by the lithographic mask; and
etching-back the spacer material to remove the spacer material from top surfaces of the plurality of patterning mandrels and to remove the spacer material from portions of the top surface of the hard mask layer, leaving sidewalls spacers surrounding the plurality of patterning mandrels.

9. A method of forming a semiconductor structure comprising:
forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors;
forming a hard mask stack over the nanosheet stack;
forming a patterning layer over the hard mask stack;
patterning a lithographic mask over the patterning layer, the lithographic mask covering (i) one or more first regions of a top surface of the patterning layer for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions of the top surface of the patterning layer for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning;
wherein the second width is less than the first width;
etching portions of the patterning layer exposed by the lithographic mask to form a plurality of patterning mandrels;
removing the lithographic mask;
depositing a spacer material over the plurality of patterning mandrels and portions of a top surface of the hard mask stack exposed by etching of the portions of the patterning layer exposed by the lithographic mask;
etching-back the spacer material to remove the spacer material from top surfaces of the plurality of patterning mandrels and to remove the spacer material from portions of the top surface of the hard mask layer, leaving sidewalls spacers surrounding the plurality of patterning mandrels; and
forming a first block mask covering at least a first subset of the plurality of patterning mandrels and the sidewall spacers surrounding the first subset of the plurality of patterning mandrels and exposing at least a second subset of the plurality of patterning mandrels and the sidewall spacers surrounding the second subset of the plurality of patterning mandrels, wherein the first subset of the plurality of patterning mandrels provide for direct printing of the one or more fins of the first width and the second subset of the plurality of patterning mandrels provide self-aligned double patterning for setting the spacing between the two or more fins of the second width.

10. The method of claim 9 , further comprising:
removing the second subset of the plurality of patterning mandrels leaving the sidewall spacers surrounding the second subset of the plurality of patterning mandrels; and
removing the first block mask.

11. The method of claim 10 , further comprising forming a second block mask covering the sidewall spacers surrounding the second subset of the plurality of patterning mandrels and exposing the first subset of the plurality of patterning mandrels and the sidewall spacers surrounding the first subset of the plurality of patterning mandrels.

12. The method of claim 11 , further comprising:
removing the sidewall spacers surrounding the first subset of the plurality of patterning mandrels exposed by the second block mask; and
removing the second block mask.

13. The method of claim 12 , further comprising etching the hard mask stack, the nanosheet stack and at least a portion of the substrate to form the one or more fins of the first width below the first subset of the plurality of patterning mandrels and to form the one or more fins of the second width below the remaining sidewall spacers.

14. The method of claim 1 , further comprising removing portions of the patterning layer exposed by the lithographic mask to form a plurality of patterning mandrels.

15. The method of claim 14 , wherein the plurality of patterning mandrels comprises a first subset of patterning mandrels corresponding to the one or more first regions defined by the lithographic mask and a second subset of patterning mandrels corresponding to the one or more second regions defined by the lithographic mask.

16. The method of claim 14 , wherein removing the portions of the patterning layer exposed by the lithographic mask to form the plurality of patterning mandrels comprises utilizing reactive-ion etching.

17. The method of claim 14 , further comprising removing the lithographic mask following removal of the portions of the patterning layer exposed by the lithographic mask to form the plurality of patterning mandrels.

Assignees

• IBM

Inventors

• Sieg Stuart
• Dechene Daniel James
• Miller Eric

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title