3D cross-point memory manufacturing process having limited lithography steps
US-10586794-B2 · Mar 10, 2020 · US
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Shepard Daniel Robert patents
Shepard Daniel Robert is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Shepard Daniel Robert |
| Total patents | 21 |
| First publication | Aug 15, 2017 |
| Latest publication | Mar 10, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Method to fabricate discrete vertical transistors
US-10381408-B2 · Aug 13, 2019 · US
Bi-directional RRAM decoder-driver
US-10255953-B2 · Apr 9, 2019 · US
Ovonic threshold switch (OTS) driver/selector uses unselect bias to pre-charge memory chip circuit and reduces unacceptable false selects
US-10192616-B2 · Jan 29, 2019 · US
Memory cell located pulse generator
US-10127979-B2 · Nov 13, 2018 · US
3D cross-point memory manufacturing process having limited lithography steps
US-10121782-B2 · Nov 6, 2018 · US
Bi-directional rram decoder-driver
US-2018137915-A1 · May 17, 2018 · US
Nano-imprinted self-aligned multi-level processing method
US-9929214-B2 · Mar 27, 2018 · US
Bi-directional RRAM decoder-driver
US-9887004-B2 · Feb 6, 2018 · US
Bi-directional rram decoder-driver
US-2017372781-A1 · Dec 28, 2017 · US
Recent patents
Latest publications not already listed above.
Ots for nvm array select lines
US-2017372779-A1 · Dec 28, 2017 · US
Dual OTS memory cell selection means and method
US-9837471-B2 · Dec 5, 2017 · US
Nano-imprinted self-aligned multi-level processing method
US-9812506-B1 · Nov 7, 2017 · US
Nano-imprinted self-aligned multi-level processing method
US-2017301729-A1 · Oct 19, 2017 · US
Dual ots memory cell selection means and method
US-2017301732-A1 · Oct 19, 2017 · US
Nano-imprinted self-aligned multi-level processing method
US-2017301677-A1 · Oct 19, 2017 · US
3d cross-point memory manufacturing process having limited lithography steps
US-2017287906-A1 · Oct 5, 2017 · US
3d cross-point memory manufacturing process having limited lithography steps
US-2017287907-A1 · Oct 5, 2017 · US
Method to fabricate discreet vertical transistors
US-2017279043-A1 · Sep 28, 2017 · US
Memory cell located pulse generator
US-2017263314-A1 · Sep 14, 2017 · US
3D cross-point memory device
US-9735151-B1 · Aug 15, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Western Digital Tech Inc | 17 |
| HGST Netherlands BV | 6 |
| HGST Netherlands BV | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10B63/80 | 13 |
| H10N70/826 | 12 |
| H10B63/24 | 12 |
| H01L45/1233 | 11 |
| H01L27/2427 | 10 |