Dual OTS memory cell selection means and method

Patent metadata

Field	Value
Publication number	US-9837471-B2
Application number	US-201615098963-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	Apr 14, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A 3D cross-point memory array includes a bitline and a word line. Both the bitline and the word line have multiple selector switches. Each switch of a corresponding bitline or word line is connected to a horizontal conductor or a vertical conductor so that a given bitline or word line has two switches, a horizontal conductor and a vertical conductor. By activating a particular horizontal conductor and vertical conductor, a specific bitline or word line is selected.

First claim

What is claimed is:

1. A 3D cross-point memory array, comprising:
a bitline;
a first selector switch coupled to the bitline;
a horizontal conductor coupled to the first selector switch, the horizontal conductor being perpendicular to the bitline;
a second selector switch coupled to the bitline;
a vertical conductor coupled to the second selector switch, the vertical conductor being perpendicular to the bitline and to the horizontal conductor, wherein the vertical conductor and the horizontal conductor are connected at the same end of the bitline; and
a memory element coupled to the bitline.

2. The 3D cross-point memory array of claim 1 , further comprising a third selector switch coupled to the memory element.

3. The 3D cross-point memory array of claim 2 , wherein the first selector switch, the second selector switch and the third selector switch are each an ovonic threshold switch.

4. The 3D cross-point memory array of claim 1 , wherein the area of the first selector switch and the area of the second selector switch are different such that when an equal current is passed through the first selector switch and the second selector switch, a greater voltage or field occurs across the selector switch having the smaller area.

5. The 3D cross-point memory array of claim 1 , wherein the volume of the first selector switch and the volume of the second selector switch are different such that when an equal current is passed through the first selector switch and the second selector switch, a greater voltage or field occurs across the selector switch having the smaller volume.

6. The 3D cross-point memory array of claim 1 , wherein the thickness of the first selector switch and the thickness of the second selector switch are different such that when an equal current is passed through the first selector switch and the second selector switch, a greater voltage or field occurs across the selector switch having the smaller thickness.

7. The 3D cross-point memory array of claim 1 , wherein the area, volume and thickness of the first selector switch and the area, volume and thickness of the second selector switch are different such that when an equal current is passed through the first selector switch and the second selector switch, a greater voltage or field occurs across the selector switch having the smaller area, volume and thickness.

8. A 3D cross-point memory array, comprising:
at least one bitline;
a first selector switch coupled to the at least one bitline;
a first horizontal conductor coupled to the first selector switch, the first horizontal conductor being perpendicular to the at least one bitline;
a second selector switch coupled to the at least one bitline;
a first vertical conductor coupled to the second selector switch, the first vertical conductor being perpendicular to the at least one bitline and to the first horizontal conductor, wherein the first vertical conductor and the first horizontal conductor are connected at the same end of the at least one bitline;
at least one word line;
a third selector switch coupled to the at least one word line;
a second horizontal conductor coupled to the third selector switch, the second horizontal conductor being perpendicular to the at least one word line;
a fourth selector switch coupled to the at least one word line;
a second vertical conductor coupled to the fourth selector switch, the second vertical conductor being perpendicular to the at least one word line and to the second horizontal conductor, wherein the second vertical conductor and the second horizontal conductor are connected at the same end of the at least one word line; and
at least one memory element coupled between the at least one bitline and the at least one word line.

9. The 3D cross-point memory array of claim 8 , further comprising a fifth selector switch coupled to the at least one memory element.

10. The 3D cross-point memory array of claim 9 , wherein the first selector switch, the second selector switch, the third selector switch, the fourth selector switch and the fifth selector switch are each an ovonic threshold switch.

11. The 3D cross-point memory array of claim 8 , wherein the first selector switch, the second selector switch, the third selector switch and the fourth selector switch are each an ovonic threshold switch.

12. A 3D cross-point memory array, comprising:
a plurality of bitlines, wherein each bitline has a first connection point and a second connection point, the first connection point and the second connection point being disposed at the same end of the bitline;
a first conductor disposed perpendicular to the plurality of bitlines;
a first selector switch coupled between each first connection point and the first conductor;
a second conductor disposed perpendicular to the plurality of bitlines and the first conductor;
a second selector switch coupled between each second connection point and the second conductor;
a plurality of word lines, wherein each word line has a third connection point and a fourth connection point, the third connection point and the fourth connection point being disposed at the same end of the word line;
a third conductor disposed perpendicular to the plurality of word lines;
a third selector switch coupled between each third connection point and the third conductor;
a fourth conductor disposed perpendicular to the plurality of word lines and the third conductor;
a fourth selector switch coupled between each fourth connection point and the fourth conductor; and
a plurality of memory elements coupled between the plurality of bitlines and the plurality of word lines.

13. The 3D cross-point memory array of claim 12 , wherein the first conductor is substantially perpendicular to the second conductor.

14. The 3D cross-point memory array of claim 12 , further comprising a fifth selector switch coupled to each memory element.

15. The 3D cross-point memory array of claim 14 , wherein the first selector switch, the second selector switch, the third selector switch, the fourth selector switch and the fifth selector switch are each an ovonic threshold switch.

16. The 3D cross-point memory array of claim 15 , wherein the plurality of word lines are perpendicular to the plurality of bitlines.

17. The 3D cross-point memory array of claim 12 , wherein the first selector switch, the second selector switch, the third selector switch and the fourth selector switch are each an ovonic threshold switch.

18. The 3D cross-point memory array of claim 17 , wherein the plurality of word lines are perpendicular to the plurality of bitlines.

19. The 3D cross-point memory array of claim 12 , wherein the plurality of word lines are perpendicular to the plurality of bitlines.

20. The 3D cross-point memory array of claim 12 , wherein:
the first conductor extends vertically within a first plane;
the second conductor extends horizontally within a second plane that is perpendicular to the first plane.

21. A 3D cross-point memory array, comprising:
a plurality of bitlines, wherein each bitline has a first connection point and a second connection point;
a first conductor;
a first selector switch coupled between each first connection point and the first conductor;
a second conductor;
a second selector switch coupled between each second connection point and the second conductor;
a plurality of word lines, wherein each word line has a third connection point and a fourth connection point;
a third conductor;
a third selector switch coupled

Assignees

• Western Digital Tech Inc

Inventors

• Shepard Daniel Robert
• Apodaca Mac D

Classifications

• H01L27/2427

  Electricity · mapped topic

• H01L27/2481 Primary

  Electricity · mapped topic

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10B63/24 Primary

  of the Ovonic threshold switching type · CPC title