3D cross-point memory manufacturing process having limited lithography steps

Patent metadata

Field	Value
Publication number	US-10121782-B2
Application number	US-201715629152-A
Country	US
Kind code	B2
Filing date	Jun 21, 2017
Priority date	Mar 24, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.

First claim

What is claimed is:

1. A method, comprising:
depositing a plurality of layers on a substrate;
forming a hard mask layer comprising a hard mask material over the plurality of layers;
forming a plurality of first trenches through the hard mask layer;
etching the plurality of first trenches down to the substrate;
filling the plurality of first trenches with a first dielectric material;
etching the first dielectric material to a level above a bottom surface of the hard mask layer;
depositing the hard mask material over a top surface of the first dielectric material;
forming a plurality of second trenches in the hard mask layer, wherein the plurality of second trenches are formed to run orthogonal to the plurality of first trenches; and
etching a plurality of holes between the plurality of first trenches and the plurality of second trenches down to the substrate.

2. The method of claim 1 , wherein the plurality of layers comprise:
a first metal layer comprising a first metal material;
a selector layer;
a memory element layer; and
a second metal layer comprising a second metal material.

3. The method of claim 2 , wherein the first metal material comprises Tungsten.

4. The method of claim 2 , wherein the selector layer comprises an ovonic threshold switch material.

5. The method of claim 2 , wherein the second metal material comprises titanium nitride.

6. The method of claim 2 , further comprising:
forming the plurality of second trenches within the selector layer, the memory element layer, and the second metal layer;
filling the plurality of holes and the plurality of second trenches formed within the selector layer, the memory element layer, and the second metal layer with a second dielectric material; and
filling the plurality of second trenches formed in the hard mask layer with the hard mask material.

7. The method of claim 6 , wherein the plurality of second trenches are formed within one or more of the selector layer, memory element layer, and second metal layer by undercut etching.

8. The method of claim 6 , further comprising:
planarizing the hard mask layer to expose the top surface of the first dielectric material;
removing the first dielectric material from the first trenches formed in the hard mask layer;
narrowing a width of the first trenches formed through the hard mask layer;
etching the first dielectric material down to a bottom surface of the second metal layer through the hard mask layer;
removing remaining first dielectric material between a top surface and the bottom surface of the second metal layer;
filling the plurality of first trenches with a third metal material; and
etching the third metal material down to the top surface of the second metal layer.

9. The method of claim 8 , wherein the third metal material comprises one or more of: the second metal material, Tungsten Nitride, and Tungsten.

10. The method of claim 8 , further comprising:
removing the hard mask material; and
depositing a third dielectric material over a top surface of the plurality of layers.

11. The method of claim 10 , further comprising:
planarizing the top surface of the plurality of layers.

12. The method of claim 8 , wherein narrowing the width of the first trenches formed through the hard mask layer comprises depositing an additional hard mask material over the hard mask layer.

13. The method of claim 8 , wherein removing the remaining first dielectric material comprises laterally etching a first wall and a second wall of the first dielectric material between the top surface and the bottom surface of the second metal layer.

14. A method, comprising:
depositing a plurality of layers on a substrate, wherein the plurality of layers comprise:
a first metal layer comprising a first metal material;
a selector layer;
a memory element layer; and
a second metal layer comprising a second metal material;

depositing hard mask material over the plurality of layers, wherein a plurality of first trenches filled with a first dielectric material extend from a level below a top surface of the hard mask material down through the plurality of layers, wherein a plurality of second trenches run orthogonal to the plurality of first trenches and comprise second trenches formed above the first trenches in the hard mask material, and wherein a plurality of holes are formed between the plurality of first trenches and the plurality of second trenches;
filling the plurality of holes and the plurality of second trenches with a second dielectric material;
planarizing the hard mask material down to expose the first trenches;
etching the first dielectric material from the first trenches to a level coplanar with a top surface of the first metal layer;
increasing a thickness of the hard mask material;
etching the first dielectric material down to a bottom surface of the second metal layer; and
laterally etching a first wall and a second wall of the first dielectric material between a top surface and the bottom surface of the second metal layer.

15. The method of claim 14 , further comprising:
filling the plurality of first trenches with a third metal material; and
etching the third metal material down to the top surface of the second metal layer.

16. The method of claim 15 , wherein the third metal material comprises one or more of Tungsten Nitride and Tungsten.

17. The method of claim 15 , further comprising:
removing the hard mask material.

18. The method of claim 17 , further comprising:
depositing a third dielectric material over a top surface of the plurality of layers; and
planarizing the top surface of the plurality of layers.

19. The method of claim 14 , further comprising:
forming a plurality of vias between the first metal layer and the second metal layer.

20. The method of claim 14 , wherein depositing the hard mask material over the first metal layer comprises:
depositing a first amount of the hard mask material over the first metal layer;
forming the first trenches through the first amount of the hard mask material;
etching the first dielectric material down to the level below a top surface of the first amount of the hard mask material; and
depositing a second amount of the hard mask material over the first amount of the hard mask material and the first dielectric material.

Assignees

• Western Digital Tech Inc

Inventors

• Apodaca Mac D
• Shepard Daniel Robert

Classifications

• H10W20/4446

  Refractory-metal alloys · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic