Bi-directional RRAM decoder-driver

Patent metadata

Field	Value
Publication number	US-9887004-B2
Application number	US-201615194678-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Jun 28, 2016
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor “on pitch” which fits between two metal lines traversing the array tile.

First claim

What is claimed is:

1. A method for creating an inverter, comprising:
selecting a word line;
applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;
selecting a bit line corresponding to the first state; and
applying a second voltage to a second inverter line to bring the second inverter line to a second state, wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, wherein at least one of i) the applying the first voltage to the first inverter line provides a third voltage to an ovonic threshold switch (OTS) coupled with the word line and the first inverter line or ii) applying the second voltage to the second inverter line provides a fourth voltage to an ovonic threshold switch (OTS) coupled with the bit line and the second inverter line.

2. The method of claim 1 , wherein the first inverter line is coupled to the word line.

3. The method of claim 1 , wherein the second inverter line is coupled to the bit line.

4. The method of claim 1 , wherein the selecting the bit line corresponding to the first state is through an n-channel.

5. The method of claim 1 , wherein the applying the first voltage to the first inverter line causes a filament formation.

6. The method of claim 5 , wherein the applying the second voltage to the second inverter line destroys the filament formation.

7. The method of claim 5 , wherein the filament formation is formed within a memory cell.

8. The method of claim 6 , wherein the memory cell comprises a RRAM material selected from the group comprising:
zinc oxide (ZnO), titanium oxide (TiO 2 ), hafnium oxide (HfO 2 ), tantalum oxide (TaO 2 ), vanadium oxide (VO 2 ), tungsten oxide (WO 2 ), zirconium oxide (ZrO 2 ), copper oxide, nickel oxide, or combinations and mixtures thereof.

9. A method for creating an inverter, comprising:
selecting a word line;
applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;
selecting a bit line corresponding to the first state; and
applying a second voltage to a second inverter line to bring the second inverter line to wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, where the applying the second voltage to the second inverter line includes: actively driving the second inverter line to the second state through a p-channel transistor.

10. The method of claim 9 , wherein the p-channel transistor is coupled to a power supply via a wired connection.

11. A method for creating an inverter, comprising:
selecting a word line;
applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;
selecting a bit line corresponding to the first state; and

applying a second voltage to a second inverter line to bring the second inverter line to wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, wherein the applying the first voltage to the first inverter line provides a third voltage to an ovonic threshold switch (OTS) coupled with the word line and the first inverter line.

12. The method of claim 11 , wherein the providing the third voltage causes a filament formation.

13. The method of claim 11 , wherein the third voltage is greater than the first voltage.

14. The method of claim 11 , wherein the third voltage turns on the OTS.

15. A method for creating an inverter, comprising:
selecting a word line;
applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;
selecting a bit line corresponding to the first state; and

applying a second voltage to a second inverter line to bring the second inverter line to wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, wherein the applying the second voltage to the second inverter line provides a fourth voltage to an ovonic threshold switch (OTS) coupled with the bit line and the second inverter line.

16. The method of claim 15 , wherein the providing the fourth voltage causes a filament destruction.

17. The method of claim 15 , wherein the fourth voltage is greater than the second voltage.

18. The method of claim 15 , wherein the fourth voltage turns on the OTS.

Assignees

• HGST Netherlands BV
• Western Digital Tech Inc

Inventors

• Otoole James Edwin
• Parkinson Ward
• Shepard Daniel Robert
• Trent Thomas Michael

Classifications

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title