3D cross-point memory device

Patent metadata

Field	Value
Publication number	US-9735151-B1
Application number	US-201615080525-A
Country	US
Kind code	B1
Filing date	Mar 24, 2016
Priority date	Mar 24, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of layers, wherein the plurality of layers comprises:
a first metal layer comprising a first metal material;
a selector layer;
a memory element layer; and
a second metal layer having a first portion and a second portion, wherein the second portion comprises a second metal material;

a plurality of first trenches, wherein the plurality of first trenches extends through the plurality of layers, wherein each of the plurality of first trenches is filled with a first dielectric material, and wherein the second portion is disposed in each of the plurality of first trenches, the second portion having rounded edges and a top surface that is coplanar with a top surface of the first portion and a bottom surface that is coplanar with a bottom surface of the first portion; and
a plurality of second trenches, wherein the plurality of second trenches extends through the selector layer, the memory element layer, and the second metal layer, wherein each of the plurality of second trenches is filled with a second dielectric material, and wherein the plurality of second trenches runs orthogonal the plurality of first trenches.

2. The memory device of claim 1 , wherein the first metal material comprises Tungsten.

3. The memory device of claim 1 , wherein the selector layer comprises an ovonic threshold switch material.

4. The memory device of claim 1 , wherein the first portion and the second portion each comprise the second metal material.

5. The memory device of claim 1 , wherein the second metal material comprises Titanium Nitride.

6. The memory device of claim 1 , wherein a first wall and a second wall of each of the plurality of first trenches are linear and parallel, and wherein a width of each of the plurality of first trenches is consistent throughout a length of each of the plurality of first trenches.

7. The memory device of claim 6 , wherein a first wall and a second wall of each of the plurality of second trenches are non-linear, and wherein each of the plurality of second trenches has a first convex portion connected to a second convex portion by a rectangular portion.

Assignees

• Western Digital Tech Inc

Inventors

• Apodaca Mac D
• Shepard Daniel Robert

Classifications

• H10W20/4446

  Refractory-metal alloys · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/0688 Primary

  Electricity · mapped topic