Nano-imprinted self-aligned multi-level processing method

Patent metadata

Field	Value
Publication number	US-9929214-B2
Application number	US-201715477739-A
Country	US
Kind code	B2
Filing date	Apr 3, 2017
Priority date	Apr 13, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F 2 3D cross-point memory array has been formed.

First claim

What is claimed is:

1. A memory device, comprising:
a first plurality of layers disposed in a first trench;
a second plurality of layers disposed in a second trench; and
a third plurality of layers disposed in a third trench, wherein a depth of the first trench and a depth of the second trench are equal, and wherein a depth of the third trench is less than the depth of the first trench; wherein the first plurality of layers comprises:
a first layer of first metal material; and
a second layer of the first metal material,

wherein the second plurality of layers comprises:
a third layer of the first metal material, wherein the third layer of the first metal material is coplanar with the first layer of the first metal material in the first trench;
a first layer of second metal material;
a fourth layer of the first metal material, wherein the fourth layer of the first metal material is coplanar with the second layer of the first metal material in the first trench; and
a second layer of the second metal material; and

wherein the third plurality of layers comprises:
a third layer of the second metal material, wherein the third layer of the second metal material is coplanar with the first layer of the second metal material; and
a fourth layer of the second metal material, wherein the fourth layer of the second metal material is coplanar with the second layer of the second metal material, wherein a depth of the first trench and a depth of the second trench are equal, and wherein a depth of the third trench is less than the depth of the first trench and the depth of the second trench.

2. The memory device of claim 1 , wherein the first metal material comprises tungsten and wherein the second metal material comprises titanium nitride.

3. The memory device according to claim 1 , wherein the memory cell has a footprint of 4F 2 where F is a minimum feature size.

4. The memory device according to claim 1 , wherein the memory cell has a footprint greater than 4F 2 where F is a minimum feature size.

5. The memory device according to claim 1 , wherein the memory cell has a footprint less than 4F 2 where F is a minimum feature size.

6. The memory device according to claim 1 , wherein at least a layer in the plurality of layers in the second trench has information storage material.

7. The memory device according to claim 6 , wherein the information storage material is a resistive random access memory material.

8. The memory device according to claim 6 , wherein the information storage material is a phase change material.

9. A memory device, comprising:
a first plurality of layers disposed in a first trench, wherein the first plurality of layers comprises:
a first layer of dielectric material; and
a second layer of the dielectric material;

a second plurality of layers disposed in a second trench, wherein the second plurality of layers comprises:
a third layer of the dielectric material, wherein the third layer of the dielectric material is partially coplanar with the second layer of the dielectric material; and

a third plurality of layers disposed in a third trench, wherein the third plurality of layers comprises:
a fourth layer of the dielectric material, wherein the third layer of the dielectric material is partially coplanar with the fourth layer of the dielectric material, wherein the first layer of the dielectric material is disposed above third layer of the dielectric material, and wherein a depth of the first trench and a depth of the second trench are equal, and wherein a depth of the third trench is less than the depth of the first trench and the depth of the second trench.

10. The memory device of claim 9 , wherein the first plurality of layers disposed in the first trench further comprising:
a first layer of first metal material; and
a second layer of the first metal material, wherein the first layer of the dielectric material is disposed between the first layer of the first metal material and the second layer of the first metal material.

11. The memory device of claim 10 , wherein the first metal material comprises tungsten.

12. The memory device of claim 9 , wherein the second plurality of layers disposed in the second trench further comprises:
a first memory device; and
a second memory device, wherein the third layer of the dielectric material is disposed between the first memory device and the second memory device.

13. The memory device of claim 9 , wherein the second plurality of layers disposed in the second trench further comprises:
a first layer of second metal material; and
a second layer of the second metal material, wherein the third layer of the dielectric material is disposed between the first layer of the second metal material and the second layer of the second metal material.

14. The memory device of claim 13 , wherein the third plurality of layers disposed in the third trench further comprises:
a third layer of the second metal material, wherein the third layer of the second metal material is coplanar with the first layer of the second metal material; and
a fourth layer of the second metal material, wherein the fourth layer of the second metal material is coplanar with the second layer of the second metal material.

15. The memory device of claim 13 , wherein the fourth layer of the dielectric material is disposed between the third layer of the second material and the fourth layer of the second metal material.

16. The memory device of claim 13 , wherein the second metal material comprises titanium nitride.

17. A memory device, comprising:
a first means for electrical contact;
a second means for electrical contact;
a first means for electrical insulation;
a second means for electrical insulation, wherein the first means for electrical contact, the second means for electrical contact, the first means for electrical insulation, and the second means for electrical insulation are disposed in a first trench;
a third means for electrical contact, wherein the third means for electrical contact is coplanar with the first means for electrical contact;
a fourth means for electrical contact;
a fifth means for electrical contact, wherein the fifth means for electrical contact is coplanar with the second means for electrical contact;
a sixth means for electrical contact;
a third means for electrical insulation, wherein the third means for electrical insulation is partially coplanar with the second means for electrical insulation, wherein the third means for electrical contact, the fourth means for electrical contact, the fifth means for electrical contact, the sixth means for electrical contact and the third means for electrical insulation are disposed in a second trench;
a seventh means for electrical contact, wherein the seventh means for electrical contact is coplanar with the fourth means for electrical contact;
an eighth means for electrical contact, wherein the eighth means for electrical contact is coplanar with the sixth means for electrical contact; and
a fourth means for electrical insulation, wherein the third means for electrical insulation is partially coplanar with the fourth means for electrical insulation, wherein the seventh means for electrical contact, the eighth means for electrical contact and the fourth means for electrical insulation are disposed in a third trench, wherein the first means for electrical insulation is disposed above third means for electrical insulation, and wherein a depth of the first trench and a depth of the second trench are equal.

18. The memory de

Assignees

• Western Digital Tech Inc

Inventors

• Apodaca Mac D
• Shepard Daniel Robert

Classifications

• H01L27/10864

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L27/11551

  Electricity · mapped topic

• H01L27/112

  Electricity · mapped topic