Memory cell located pulse generator

Patent metadata

Field	Value
Publication number	US-10127979-B2
Application number	US-201615068213-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Mar 11, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

The present disclosure generally relates to a memory cell and methods for generating a pulse within the memory cell. As such, a geometric arrangement of transistors is disclosed that allows the transistor pulse signal generator circuit to precharge both sides of the memory cell and, subsequently, bring opposite sides of the memory cell quickly to different voltages. The circuit and wiring fabrication provided, when combined with a related transistor manufacturing process, yields pulse generating logic at the memory cell to enable the formation of a well-defined pulse while fitting within the 4F 2 footprint of the memory cell. As such, the speed and pulse shape requirements of PCM, MRAM, other such cross-point memory technologies, sensor arrays, and/or pixel displays may take advantage of the reduced RC circuitry delays.

First claim

What is claimed is:

1. A memory device, comprising:
a bit line;
a word line;
a memory cell coupled between the bit line and the word line;
a first transistor having a first source electrode, a first drain electrode, and a first gate electrode;
a second transistor having a second source electrode, a second drain electrode, and a second gate electrode;
wherein the first gate electrode is coupled to the second gate electrode, the first source electrode is coupled to a first source voltage potential above a ground potential, the second source electrode is coupled to a second source voltage potential above the ground potential, and the first drain electrode and the word line are coupled to a same node.

2. The memory device of claim 1 , further comprising a third transistor comprising a third source electrode coupled to the first drain electrode.

3. The memory device of claim 1 , further comprising a fourth transistor comprising a fourth source electrode coupled to the second drain electrode.

4. The memory device of claim 1 , further comprising:
a third transistor comprising a third source electrode coupled to the first drain electrode;
a fourth transistor comprising a source electrode coupled to the second drain electrode and the bit line; and
a resistor coupled between the third transistor and the fourth transistor.

5. The memory device of claim 1 , further comprising a select pre-charge coupled to the first gate electrode and the second gate electrode.

6. The memory device of claim 1 , wherein the memory cell comprises a 4F 2 footprint.

7. A memory array, comprising:
a plurality of memory devices, including a first memory device and a second memory device, each memory device comprising:
a bit line;
a word line;
a memory cell coupled between the bit line and the word line;
a first transistor having a first source electrode, a first drain electrode, and a first gate electrode;
a second transistor having a second source electrode, a second drain electrode, and a second gate electrode;
a third transistor having a third source electrode, a third drain electrode, and a third gate electrode; and
a fourth transistor having a fourth source electrode, a fourth drain electrode, and a fourth gate electrode,
wherein the first gate electrode is coupled to the second gate electrode, the first source electrode is coupled to a first voltage source, the second source electrode is coupled to a second voltage source, the third transistor of the first memory device is coupled to the fourth transistor of the second memory device, and the first drain electrode, the third source electrode and the word line are coupled to a common node.

8. The memory array of claim 7 , wherein the first drain electrode of the first memory device is coupled to the third source electrode of the first memory device.

9. The memory array of claim 7 , wherein the second drain electrode of the first memory device is coupled to the fourth source electrode of the first memory device.

10. The memory array of claim 7 , wherein each memory device further comprises a resistor coupled between the third transistor and the fourth transistor.

11. The memory array of claim 7 , wherein each memory device further comprises a select pre-charge coupled to the first gate electrode and the second gate electrode.

12. The memory array of claim 7 , wherein each memory cell comprises a 4F 2 footprint.

13. A pulse generator circuit, comprising:
a bit-line drive transistor; and
a word-line drive transistor, wherein:
the bit-line drive transistor is configured to drive a first current on a bit line of a memory cell and the word-line drive transistor is configured to drive a second current on a word line of the memory cell, the second current separate from the first current, and
the bit-line drive transistor and the word-line drive transistor are activated by a same gate control signal.

14. The pulse generator circuit of claim 13 , wherein a control gate of the bit-line drive transistor and a control gate of the word-line drive transistor are operatively coupled to the same gate control signal.

15. The pulse generator circuit of claim 13 , wherein:
the bit-line drive transistor comprises:
a source electrode operatively coupled to a first source voltage potential, and
a drain electrode operatively coupled to a bit line node, the bit line node operatively coupled to the bit line of the memory cell; and

the word-line drive transistor comprises:
a source electrode operatively coupled to a second source voltage potential, and
a drain electrode operatively coupled to a word line node, the word line node operatively coupled to the word line of the memory cell.

16. The pulse generator circuit of claim 15 , further comprising a bit-line control transistor, comprising:
a source electrode operatively coupled to the bit line node, and
a drain electrode operatively coupled to a first ground node.

17. The pulse generator circuit of claim 15 , further comprising a word-line control transistor, comprising:
a source electrode operatively coupled to the word line node, and
a drain electrode operatively coupled to a second ground node.

18. The pulse generator circuit of claim 13 , further comprising:
a first control transistor comprising:
a source electrode operatively coupled to the bit line of the memory cell and a drain electrode of the bit-line drive transistor,
a drain electrode operatively coupled to ground, and
a control gate operatively coupled to a first select line;

a second control transistor comprising:
a source electrode operatively coupled to the word line of the memory cell and a drain electrode of the word-line drive transistor,
a drain electrode operatively coupled to ground, and
a control gate operatively coupled to a second select line; and

a resistor operatively coupled between the first control transistor and the second control transistor.

19. The pulse generator circuit of claim 13 , wherein:
a drain electrode of the bit-line drive transistor is operatively coupled to the bit line of the memory cell and a source node of a first control transistor; and
a drain electrode of the word-line drive transistor is operatively coupled to the word line of the memory cell and a source node of a second control transistor.

20. The pulse generator circuit of claim 19 , wherein:
a source node of the bit-line drive transistor is operatively coupled to a first voltage source;
a source node of the word-line drive transistor is operatively coupled to a second voltage source;
a gate electrode of the bit-line drive transistor and a gate electrode of the word-line drive transistor are operatively coupled to the same gate control signal;
drain electrodes of the first control transistor and the second control transistor are operatively coupled to ground;
a gate electrode of the first control transistor is operatively coupled to a first select line; and
a gate electrode of the second control transistor is operatively coupled to a second select line.

Assignees

• Western Digital Tech Inc

Inventors

• Apodaca Mac D
• Shepard Daniel Robert

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L45/06

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• G11C11/1675

  Writing or programming circuits or methods · CPC title